Data Sheet

ADMFM2000

THEORY OF OPERATION

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The ADMFM2000 is a dual-channel, microwave downconverter.

Each downconversion path consists of an LNA, mixer, filter, DSA, IF

amplifier, and a single LO input that drives both mixers.

Figure 59. ADMFM2000 Simplified Block Diagram

LNA

The ADMFM2000 has a wideband LNA in each channel that oper-

ates between 5 GHz and 32 GHz. The LNAs are self-biased with

a required single 5 V supply. Inputs and outputs are internally

matched to 50 Ω and have internal DC blocking capacitors.

Each LNA also has gain control capability using the

VGG_RFAMP_1 and VGG_RFAMP_2 pins corresponding to each

channel. These pins are internally self-biased and must normally be

left open.

MIXER

The ADMFM2000 has a double-balanced mixer in each channel.

These mixers down convert the RF from 5 GHz and 32 GHz to

a corresponding IF of 0.5 GHz and 8 GHz. These mixers are

passive devices and require no external biasing components or RF

matching circuitry. The mixers in the ADMFM2000 operate well with

a LO drive level of 6 dBm at the LO input pin.

LO

A common LO input operates from 7 GHz to 30 GHz and is

split to feed separate buffer amplifiers for each channel. These

amplifiers drive separate mixers in each channel. The buffer ampli-

fiers also have gain control using the VGG_LOAMP_1 and the

VGG_LOAMP_2 pins, one for each channel. The VGG_LOAMP_x

pins are internally self-biased and must normally be left open. The

typical LO drive level at the LO input pin is 6 dBm.

SWITCH

The ADMFM2000 has a broadband SPDT RF switch in each

channel that can be used to bypass the mixer. The SPDTs require

negative control voltages at the control pins (SW_CHx_CTRL_A

and SW_CHx_CTRL_B, x = 1 or 2). Depending on the logic level

applied to those control pins, the IF path is either connected to

the mixer or to the RF_BYPASS_IN pin (see Figure 59 and Table

7). The required logic level for operating mode on Channel 2 is

opposite to the required logic level on Channel 1.

Table 7. Switch Control Truth Table for SW1_CTRL_A, SW1_CTRL_B, SW2_CTRL_A, and SW2_CLRL_B

Digital Control Inputs1

RF Paths

SWx_CTRL_A

SWx_CTRL_B

Channel 1 Status

Channel 2 Status

High

Low

Direct IF mode

Mixer mode

Low

High

Mixer mode

Direct IF mode

1 Refer to logic input in Table 1 for the logic level high and low detailed in Table 7.