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M93C46 数据表(PDF) 21 Page - STMicroelectronics |
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M93C46 数据表(HTML) 21 Page - STMicroelectronics |
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21 / 31 page ![]() 21/31 M93C86, M93C76, M93C66, M93C56, M93C46 Table 22. AC Characteristics (M93Cx6-W, Device Grade 7 or 3) Note: 1. tCHCL + tCLCH ≥ 1 / fC. 2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles. Test conditions specified in Table 13. and Table 10. Symbol Alt. Parameter Min. Max. Unit fC fSK Clock Frequency D.C. 2 MHz tSLCH Chip Select Low to Clock High 50 ns tSHCH tCSS Chip Select Set-up Time 50 ns tSLSH (2) tCS Chip Select Low to Chip Select High 200 ns tCHCL (1) tSKH Clock High Time 200 ns tCLCH (1) tSKL Clock Low Time 200 ns tDVCH tDIS Data In Set-up Time 50 ns tCHDX tDIH Data In Hold Time 50 ns tCLSH tSKS Clock Set-up Time (relative to S) 50 ns tCLSL tCSH Chip Select Hold Time 0 ns tSHQV tSV Chip Select to Ready/Busy Status 200 ns tSLQZ tDF Chip Select Low to Output Hi-Z 100 ns tCHQL tPD0 Delay to Output Low 200 ns tCHQV tPD1 Delay to Output Valid 200 ns tW tWP Erase/Write Cycle time 5 ms |
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