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CS42435-DMZ 数据表(PDF) 21 Page - Cirrus Logic

部件名 CS42435-DMZ
功能描述  108 dB, 192 kHz 4-In, 8-Out TDM CODEC
PDF  58 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS42435-DMZ 数据表(HTML) 21 Page - Cirrus Logic

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21
CS42435
SWITCHING SPECIFICATIONS - ADC/DAC PORT
(Inputs: Logic 0 = DGND, Logic 1 = VLS, ADC_SDOUT CLOAD = 15 pF.)
Notes:
16. After powering up the CS42435, RST should be held low after the power supplies and clocks are settled.
17. See Table 5 on page 42 for suggested MCLK frequencies.
18. VLS is limited to nominal 2.5 V to 5.0 V operation only.
19. ADC does not meet timing specification for Quad-Speed Mode.
Parameters
Symbol
Min
Max
Units
Slave Mode
RST pin Low Pulse Width
(Note 16)
1
-ms
MCLK Frequency
0.512
50
MHz
MCLK Duty Cycle
(Note 17)
45
55
%
Input Sample Rate (FS pin)
Single-Speed Mode
Double-Speed Mode (Note 18)
Quad-Speed Mode (Note 19)
Fs
Fs
Fs
4
50
100
50
100
200
kHz
kHz
kHz
SCLK Duty Cycle
45
55
%
SCLK High Time
tsckh
8-
ns
SCLK Low Time
tsckl
8-
ns
FS Rising Edge to SCLK Rising Edge
tfss
5-
ns
SCLK Rising Edge to FS Falling Edge
tfsh
16
-
ns
DAC_SDIN Setup Time Before SCLK Rising Edge
tds
3-
ns
DAC_SDIN Hold Time After SCLK Rising Edge
tdh
5-
ns
DAC_SDIN Hold Time After SCLK Rising Edge
tdh1
5-
ns
ADC_SDOUT Hold Time After SCLK Rising Edge
tdh2
10
-
ns
ADC_SDOUT Valid Before SCLK Rising Edge
tdval
15
-
ns
ADC_SDOUT
DAC_SDIN
t
ds
SCLK
(input)
FS
(input)
MSB
t
dh1
t
sckh
t
sckl
t
dval
MSB-1
MSB
MSB-1
t
fsh
t
fss
t
dh2
Figure 5. TDM Serial Audio Interface Timing



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