M93C76-RBN3TP datasheet(12/31 Pages) STMICROELECTRONICS

12 / 31 page

M93C86, M93C76, M93C66, M93C56, M93C46

12/31

READY/BUSY STATUS

While the Write or Erase cycle is underway, for a

WRITE, ERASE, WRAL or ERAL instruction, the

Busy signal (Q=0) is returned whenever Chip Se-

lect Input (S) is driven High. (Please note, though,

that there is an initial delay, of tSLSH, before this

status information becomes available). In this

state, the M93Cx6 ignores any data on the bus.

When the Write cycle is completed, and Chip Se-

lect Input (S) is driven High, the Ready signal

(Q=1) indicates that the M93Cx6 is ready to re-

ceive the next instruction. Serial Data Output (Q)

remains set to 1 until the Chip Select Input (S) is

brought Low or until a new start bit is decoded.

INITIAL DELIVERY STATE

The device is delivered with all bits in the memory

array set to 1 (each byte contains FFh).

COMMON I/O OPERATION

Serial Data Output (Q) and Serial Data Input (D)

can be connected together, through a current lim-

iting resistor, to form a common, single-wire data

bus. Some precautions must be taken when oper-

ating the memory in this way, mostly to prevent a

short circuit current from flowing when the last ad-

dress bit (A0) clashes with the first data bit on Se-

rial Data Output (Q). Please see the application

note

AN394 for details.

CLOCK PULSE COUNTER

In a noisy environment, the number of pulses re-

ceived on Serial Clock (C) may be greater than the

number delivered by the master (the microcontrol-

ler). This can lead to a misalignment of the instruc-

tion of one or more bits (as shown in Figure 7.) and

may lead to the writing of erroneous data at an er-

roneous address.

To combat this problem, the M93Cx6 has an on-

chip counter that counts the clock pulses from the

start bit until the falling edge of the Chip Select In-

put (S). If the number of clock pulses received is

not the number expected, the WRITE, ERASE,

ERAL or WRAL instruction is aborted, and the

contents of the memory are not modified.

The number of clock cycles expected for each in-

struction, and for each member of the M93Cx6

family, are summarized in Table 5. to Table 7.. For

example, a Write Data to Memory (WRITE) in-

struction on the M93C56 (or M93C66) expects 20

clock cycles (for the x8 organization) from the start

bit to the falling edge of Chip Select Input (S). That

is:

1 Start bit

+ 2 Op-code bits

+ 9 Address bits

+ 8 Data bits

Figure 7. Write Sequence with One Clock Glitch

AI01395

An-1

WRITE

START

"1"

"0"

Glitch

An-2

ADDRESS AND DATA

ARE SHIFTED BY ONE BIT

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