PAC7112 datasheet(17/56 Pages) FREESCALE

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ElectricalCharacteristics

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2

Preliminary

Freescale Semiconductor

The capacitance CP should be chosen in the range of:

Eqn. 14

The stabilization delays shown in Table 20 are dependant on PLL operational settings and external

component selection (for example, the crystal and XFC filter).

3.8.2.1

Jitter Information

With each transition of the clock fCMP, the deviation from the reference clock fREF is measured and input

voltage to the VCO is adjusted accordingly. The adjustment is done continuously with no abrupt changes

in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the

control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as

illustrated in Figure 4. It is important to note that the pre-scaler used by timers and serial modules will

eliminate the effect of PLL jitter to a large extent.

Figure 4. Jitter Definitions

The relative deviation of tNOM is at its maximum for one clock period, and decreases towards zero for

larger number of clock periods (N). Thus, jitter is defined as:

Eqn. 15

For N

< 100, the following equation is a good fit for the maximum jitter:

Eqn. 16

Figure 5. Maximum Bus Clock Jitter Approximation

≤≤

tMIN1

N–1

tNOM

tMAX1

tMIN(N)

tMAX(N)

()

max 1

MAX N

()

NOM

⋅

--------------------

–1

MIN N

()

NOM

⋅

--------------------

–

⎝⎠

⎛⎞

()

--------

J(N)

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