SN74LVC74APWR datasheet(3/40 Pages) TI1

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4 Pin Configuration and Functions

Figure 4-1. D, DB, J, PW, NS, or W Package 14-Pin

SOIC, SSOP, CDIP, TSSOP, SO, or CFP (Top View)

2CLR

2CLK

2PRE

1CLK

1PRE

Figure 4-2. BQA or RGY Package 14-Pin WQFN or

VQFN With Exposed Thermal Pad (Top View)

Figure 4-3. FK Package 20-Pin LCCC (Top View)

Table 4-1. Pin Functions

I/O

DESCRIPTION

NAME

CDIP, CFP, PDIP, SO, SOIC,

SSOP, TSSOP, VQFN

LCCC

1CLK

Channel 1 clock input

1 CLR

Channel 1 clear input. Pull low to set Q output low.

Channel 1 data input

1 PRE

Channel 1 preset input. Pull low to set Q output high.

Channel 1 output

1 Q

Channel 1 inverted output

2CLK

Channel 2 clock input

2 CLR

Channel 2 clear input. Pull low to set Q output low.

Channel 2 data input

2 PRE

Channel 2 preset input. Pull low to set Q output high.

Channel 2 output

2 Q

Channel 2 Inverted output

GND

—

Ground

—

1, 5, 7, 11, 15, 17

—

No connect

VCC

—

Supply

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SN54LVC74A, SN74LVC74A

SCAS287V – JANUARY 1993 – REVISED MAY 2024

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