VM6101

Functional description

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Figure 4.

PWM duty cycle versus illumination

2.4

Two-wire serial interface

The VM6101 two-wire serial interface supports the following features:

●

Standard-mode (100 kHz) I²C slave controller supporting 8-bit addressing

(7-bit address = 0x10 or 0010 000). SMBus compliant.

●

Data and clock deglitching filters (double sampling)

●

8-bit index, i.e. 256 on-chip register address space

●

Multiple read or write with index auto-increment

●

Alternate address (0x11) selectable

2.4.1

Message types

The VM6101 registers are accessed by serial bus byte-oriented transactions. The following

message types are supported:

●

Master write:

<S> <addr><w><A> <index><A> <data><A>[<data><A>...<data><A>]<P>

●

Master read:

<S> <addr><r><A> [<data><A>...<data><A>]<data><nA><P>

●

Combined format:

<S> <addr><w><A> <index><A>

<Sr> <addr><r><A> [<data><A>...<data><A>]<data><nA><P>

where:

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1E+00

10E+00

100E+00

1E+03

10E+03

100E+03

Illumination (lx)

PWM_SENS = 18

PWM_SENS = 9

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1E+00

10E+00

100E+00

1E+03

10E+03

100E+03

Illuminance (lx)

PWM_SENS = 18

PWM_SENS = 9