IA188EM-PTQ100I-R datasheet(13/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

SDEC (bit 11) – Source Decrement, when set to 1, automatically decrements the destination address

after each transfer. The address is decremented by 1 or 2, depending on the byte/word bit (Bn/W, bit

0). The address does not change if the increment and decrement bits are set to the same value (00b or

11b).

SINC (bit 10) – Source Increment, when set to 1, automatically increments the destination address

after each transfer. The address is incremented by 1 or 2, depending on the byte/word bit (Bn/W, bit

0). The address does not change if the increment and decrement bits are set to the same value (00b or

11b).

TC (bit 9) – Terminal Count. The DMA decrements the transfer count for each DMA transfer. When

TC is set to 1, the source or destination synchronized DMA transfers terminate when the count reaches

0, but when TC is set to 0, source or destination synchronized DMA transfers do not terminate when

the count reaches 0. Unsynchronized DMA transfers always end when the count reaches 0,

irrespective of the setting of this bit.

INT (bit 8) – Interrupt. The DMA channel generates an interrupt request on completion of the transfer

count when this bit is set to 1. However, for an interrupt to be generated, the TC bit must also be set

to 1.

SYN1-SYN0 (bits 7-6) – Synchronization Type bits select channel synchronization as shown in the

following table. The value of these bits is ignored if TDRQ (bit 4) is set to 1. A processor reset

causes these bits to be set to 11b.

SYN1

SYN0

Sync Type

Unsynchronized

Source Synchronized

Destination Synchronized

Reserved

P (bit 5) – Relative Priority. Selects high priority for this channel relative to the other channel during

simultaneous transfers when set to 1.

TDRQ (bit 4) - Timer 2 Synchronization. Enables DMA requests from timer 2, when set to 1, but

disables DMA requests from timer 2 when set to 0.

EXT (bit 3) – Reserved.

CHG (bit 2) – Change Start Bit. This bit must be set to 1, to allow modification of the ST bit during a

write. During a write, when CHG is set to 0, ST is not changed when writing the control word. The

result of reading this bit is always 0.

3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com

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