PHT6N06LT datasheet(4/9 Pages) PHILIPS

4 / 9 page

Philips Semiconductors

Product specification

TrenchMOS

™ transistor

PHT6N06LT

Logic level FET

Fig.1. Normalised power dissipation.

PD% = 100

⋅P

D/PD 25 ˚C = f(Tsp)

Fig.2. Normalised continuous drain current.

ID% = 100

⋅I

D/ID 25 ˚C = f(Tsp); conditions: VGS ≥ 5 V

Fig.3. Safe operating area. T

sp = 25 ˚C

D & IDM = f(VDS); IDM single pulse; parameter tp

Fig.4. Transient thermal impedance.

th j-sp = f(t); parameter D = tp/T

Fig.5. Typical output characteristics, T

j = 25 ˚C.

D = f(VDS); parameter VGS

Fig.6. Typical on-state resistance, T

j = 25 ˚C.

DS(ON) = f(ID); parameter VGS

100

120

140

Tmb / C

PD%

Normalised Power Derating

120

110

100

1E-07

1E-05

1E-03

1E-01

1E+01

t / s

Zth / (K/W)

1E+02

3E+01

1E+01

3E+00

1E+00

3E-01

1E-01

3E-02

1E-02

0.5

0.2

0.1

0.05

0.02

D =

BUKX8150-55

100

120

140

Tmb / C

ID%

Normalised Current Derating

120

110

100

02468

2.2

2.4

2.6

2.8

3.0

3.2

3.4

VGS = 3.6 V

3.8

Drain current, ID (A)

Drain-source voltage, VDS (V)

VDS/V

ID/A

1 us

10 us

100 us

1 ms

10 ms

100 ms

tp =

0.1

100

110

RDS(ON) = VDS/ID

BUKX8150-55

123

4567

100

150

200

250

300

350

400 RDS(ON)mOhm

ID/A

3.6

3.4

3.2

January 1998

Rev 1.100

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