PHT8N06LT datasheet(4/9 Pages) PHILIPS

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Philips Semiconductors

Product specification

TrenchMOS

™ transistor

PHT8N06LT

Logic level FET

Fig.1. Normalised power dissipation.

PD% = 100

⋅P

D/PD 25 ˚C = f(Tsp)

Fig.2. Normalised continuous drain current.

ID% = 100

⋅I

D/ID 25 ˚C = f(Tsp); conditions: VGS ≥ 5 V

Fig.3. Safe operating area. T

sp = 25 ˚C

D & IDM = f(VDS); IDM single pulse; parameter tp

Fig.4. Transient thermal impedance.

th j-sp = f(t); parameter D = tp/T

Fig.5. Typical output characteristics, T

j = 25 ˚C.

D = f(VDS); parameter VGS

Fig.6. Typical on-state resistance, T

j = 25 ˚C.

DS(ON) = f(ID); parameter VGS

100

120

140

Tmb / C

PD%

Normalised Power Derating

120

110

100

1.0E-06

0.0001

0.01

100

0.01

0.1

100

Zth/ (K/W)

t/s

0.5

0.2

0.1

0.05

0.02

D =

100

120

140

Tmb / C

ID%

Normalised Current Derating

120

110

100

02468

VGS = 5.0 V

4.6

4.0

3.6

3.2

3.0

2.6

2.4

Drain current, ID (A)

Drain-source voltage, VDS (V)

100

0.1

100

VDS/V

RDS(ON) = VDS/ID

ID/A

tp =

1 us

10us

100 us

1 ms

10ms

100ms

10152025

100

105

110

115

RDS(ON)/mOhm

4.2

4.4

4.6

4.8

ID/A

January 1998

Rev 1.100

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