数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

LS7060C 数据表(PDF) 3 Page - LSI Computer Systems

部件名 LS7060C
功能描述  32 BIT BINARY UP COUNTER WITH BYTE MULTIPLEXED THREE-STATE OUTPUTS
PDF  7 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  LSI [LSI Computer Systems]
网页  http://www.lsicsi.com
标志 LSI - LSI Computer Systems

LS7060C 数据表(HTML) 3 Page - LSI Computer Systems

  LS7060C Datasheet HTML 1Page - LSI Computer Systems LS7060C Datasheet HTML 2Page - LSI Computer Systems LS7060C Datasheet HTML 3Page - LSI Computer Systems LS7060C Datasheet HTML 4Page - LSI Computer Systems LS7060C Datasheet HTML 5Page - LSI Computer Systems LS7060C Datasheet HTML 6Page - LSI Computer Systems LS7060C Datasheet HTML 7Page - LSI Computer Systems  
Zoom Inzoom in Zoom Outzoom out
 3 / 7 page
background image
DYNAMIC ELECTRICAL CHARACTERISTICS:
(VDD = +5V ± 5%, VSS = 0V, TA = 0˚C to +70˚C unless otherwise noted.)
PARAMETER
SYMBOL
MIN
MAX
UNIT
CONDITIONS
Count Frequency
fc
DC
50
MHz
-
(All Count inputs)
Count Pulse Width
tCPW
10
-
ns
Measured at 50% point,
(All Count Inputs)
Max tr, tf = 1ns
Count Ripple Time
tCR
-
20
ns
Transition from 32 ones to 32 zeros
from negative edge of count pulse
Reset Pulse Width
tRPW
20
-
ns
Measured at 50% point
(All Counter Stages
Max tr, tf = 10ns
Fully Reset)
RESET Removal Time
tRR
-
10
ns
Measured from RESET signal at VIH
(Reset Removed From
All Counter Stages)
SCAN Frequency
fSC
-
10
MHz
SCAN Pulse Width
tSCPW
50
-
ns
Measured at 50% point
Max tr, tf = 10ns
SCAN RESET/LOAD
tRSCPW
10
-
ns
Measured at 50% point
Pulse Width
Max tr, tf = 5ns
(All latches loaded and
Scan Counter Reset to
Least Significant Byte)
SCAN RESET/LOAD
tRSCR
-
10
ns
Measured from
Removal Time
SCAN RESET/LOAD at VIH
(Reset Removed from
Scan Counter; Load
Command Removed
From Latches)
Output Disable
tDOD
-
5
ns
Transition to Output High
Delay Time
Impedance State Measured
(B0 - B7)
From Scan at VIL or
ENABLE at VIH
Output ENABLE
tDOE
-
5
ns
Transition to Valid On State
Delay Time
Measured from Scan at VIH
(B0 - B7)
and ENABLE at VIL; Delay to
Valid Data Levels for COL = 10pF
and one TTL Load or Valid Data
Currents for High Capacitance Loads
Output Delay Time
tDCE
-
10
ns
Negative Transition from Scan at VIL
CASCADE ENABLE
and ST5 of Scan Counter or Positive
Transition From SCAN RESET/LOAD at
VIL to Valid Data Levels for COL = 12pF
and one TTL Load
SYMBOL
MIN
MAX
UNIT
CONDITIONS
INPUT CURRENT
*SCAN RESET/LOAD
IIH
-
-3.5
µA
VDD = Max, VIH = +3.5V
IIL
-
-5
µA
VDD = Max, VIL = 0V
**All Count inputs
IIH
-
5
µA
VDD = Max, VIH = +3.5V
IIL
-
1
µA
VDD = Max, VIL = 0.35V
*Input has internal pull-up resistor to VDD
** Inputs have internal pull-down resistor to VSS
7060C/61C-121901-3



Html Pages

1 2 3 4 5 6 7


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com