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LT1374

1374fb

APPLICATIONS INFORMATION

What About a Resistor in the Compensation Network?

It is common practice in switching regulator design to

add a “zero” to the error amplifier compensation to

increase loop phase margin. This zero is created in the

external network in the form of a resistor (RC) in series

with the compensation capacitor. Increasing the size of

this resistor generally creates better and better loop

stability, but there are two limitations on its value. First,

the combination of output capacitor ESR and a large

value for RC may cause loop gain to stop rolling off

altogether, creating a gain margin problem. An approxi-

mate formula for RC where gain margin falls to zero is:

R Loop

ESR

OUT

Gain = 1

()=()( )( )( )

242

GMP = Transconductance of power stage = 5.3A/V

GMA = Error amplifier transconductance = 2(10–3)

ESR = Output capacitor ESR

2.42 = Reference voltage

With VOUT = 5V and ESR = 0.03Ω, a value of 6.5k for RC

would yield zero gain margin, so this represents an upper

limit. There is a second limitation however which has

nothing to do with theoretical small signal dynamics.

This resistor sets high frequency gain of the error ampli-

fier, including the gain at the switching frequency. If

switching frequency gain is high enough, output ripple

voltage will appear at the VC pin with enough amplitude

to muck up proper operation of the regulator. In the

marginal case,

subharmonic switching occurs, as evi-

denced by alternating pulse widths seen at the switch

node. In more severe cases, the regulator squeals or

hisses audibly even though the output voltage is still

roughly correct. None of this will show on a theoretical

Bode plot because Bode is an amplitude insensitive

analysis.

Tests have shown that if ripple voltage on the VC

is held to less than 100mVP-P, the LT1374 will be well

behaved. The formula below will give an estimate of VC

ripple voltage when RC is added to the loop, assuming

that RC is large compared to the reactance of CC at

500kHz.

ESR

VL f

C RIPPLE

OUT

(

) =

()( ) −

()( )( )

GMA = Error amplifier transconductance (2000µMho)

If a computer simulation of the LT1374 showed that a

series compensation resistor of 3k gave best overall loop

response, with adequate gain margin, the resulting VC pin

ripple voltage with VIN = 10V, VOUT = 5V, ESR = 0.1Ω,

L = 10

µH, would be:

C RIPPLE

(

)

−

()





−

()( )( )

()













2 10

10 5 0 1 2 4

10 10 10

500 10

0 144

•.

••

This ripple voltage is high enough to possibly create

subharmonic switching. In most situations a compromise

value (< 2k in this case) for the resistor gives acceptable

phase margin and no subharmonic problems. In other

cases, the resistor may have to be larger to get acceptable

phase response, and some means must be used to control

ripple voltage at the VC pin. The suggested way to do this

is to add a capacitor (CF) in parallel with the RC/CC network

on the VC pin. Pole frequency for this capacitor is typically

set at one-fifth of switching frequency so that it provides

significant attenuation of switching ripple, but does not

add unacceptable phase shift at loop unity-gain frequency.

With RC = 3k,

= ()( )( )= 





 ()

500 10

531

•

How Do I Test Loop Stability?

The “standard” compensation for LT1374 is a 1.5nF

capacitor for CC, with RC = 0. While this compensation will

work for most applications, the “optimum” value for loop

compensation components depends, to various extent, on

parameters which are not well controlled. These include

inductor value (

±30% due to production tolerance, load

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