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MPC866 数据表(PDF) 51 Page - Freescale Semiconductor, Inc |
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MPC866 数据表(HTML) 51 Page - Freescale Semiconductor, Inc |
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51 / 96 page  MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 51 CPM Electrical Characteristics Figure 46. Port C Interrupt Detection Timing 12.3 IDMA Controller AC Electrical Specifications Table 18 shows the IDMA controller timings as shown in Figure 47 through Figure 50. Figure 47. IDMA External Requests Timing Diagram Table 18. IDMA Controller Timing Num Characteristic All Frequencies Unit Min Max 40 DREQ setup time to clock high 7 — ns 41 DREQ hold time from clock high 3 — ns 42 SDACK assertion delay from clock high — 12 ns 43 SDACK negation delay from clock low — 12 ns 44 SDACK negation delay from TA low — 20 ns 45 SDACK negation delay from clock high — 15 ns 46 TA assertion to falling edge of the clock setup time (applies to external TA)7 — ns Port C 35 36 (Input) 41 40 DREQ (Input) CLKO (Output) |
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