MPC885ZP66 datasheet(73/92 Pages) FREESCALE

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MPC885/MPC880 Hardware Specifications, Rev. 3

Freescale Semiconductor

FEC Electrical Characteristics

Table 35 provides information on the MII and RMII transmit signal timing.

Figure 73 shows the MII transmit signal timing diagram.

Figure 73. MII Transmit Signal Timing Diagram

15.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL)

Table 36 provides information on the MII async inputs signal timing.

Table 35. MII Transmit Signal Timing

Num

Characteristic

Min

Max

Unit

MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid

—

MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid

—

M20_R

MII

RMII_TXD[1:0], RMII_TX_EN to RMII_REFCLK setup

—

M21_R

MII

RMII_TXD[1:0], RMII_TX_EN data hold from RMII_REFCLK rising

edge

2—

MII_TX_CLK and RMII_REFCLK pulse width high

35%

65%

MII_TX_CLK or

RMII_REFCLK

period

MII_TX_CLK and RMII_REFCLK pulse width low

35%

65%

MII_TX_CLK or

RMII_REFCLK

period

Table 36. MII Async Inputs Signal Timing

Num

Characteristic

Min

Max

Unit

MII_CRS, MII_COL minimum pulse width

1.5

—

MII_TX_CLK period

MII_TX_CLK (input)

MII_TXD[3:0] (outputs)

MII_TX_EN

MII_TX_ER

RMII_REFCLK

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