 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
MPC8280VRB 数据表(PDF) 18 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MPC8280VRB 数据表(HTML) 18 Page - Freescale Semiconductor, Inc |
|
|
18 / 80 page  MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7 18 Freescale Semiconductor AC Electrical Characteristics Figure 7 shows TDM input and output signals. Figure 7. TDM Signal Diagram Figure 8 shows PIO and timer signals. Figure 8. PIO and Timer Signal Diagram Serial CLKin TDM input signals TDM output signals sp20 sp21 sp40/sp41 Note: There are four possible TDM timing conditions: 1. Input sampled on the rising edge and output driven on the rising edge (shown). 2. Input sampled on the rising edge and output driven on the falling edge. 3. Input sampled on the falling edge and output driven on the falling edge. 4. Input sampled on the falling edge and output driven on the rising edge. Sys clk PIO/IDMA/TIMER[TGATE assertion] input signals IDMA output signals sp22 sp23 sp42/sp43 TIMER(sp42/43)/ PIO(sp42a/sp43a) sp42a/sp43a output signals sp42/sp43 TIMER input signal [TGATE deassertion] sp22 sp23 Note: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge. (See note) (See note) |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
