| 数据搜索系统,热门电子元器件搜索 |
|
MP8040DN 数据表(PDF) 2 Page - Monolithic Power Systems |
|
|
|||||||||||||||||||||||||||||
MP8040DN 数据表(HTML) 2 Page - Monolithic Power Systems |
|
2 / 8 page ![]() MP8040 – HIGH CURRENT INTEGRATED HALF BRIDGE + DRIVER MP8040 Rev. 1.5 www.MonolithicPower.com 2 5/3/2005 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2005 MPS. All Rights Reserved. TM PACKAGE REFERENCE Part Number* Package Temperature MP8040DN SOIC8N (Exposed Pad) –40 °C to +85°C * For Tape & Reel, add suffix –Z (eg. MP8040DN–Z) For Lead Free, add suffix –LF (eg. MP8040DN–LF–Z) ABSOLUTE MAXIMUM RATINGS (1) SP Supply Voltage (VSP).............................. 28V SW Pin Voltage .............................. –0.3V to VSP SW to BS ....................................... –0.3V to +6V Voltage at All Other Pins ............... –0.3V to +6V Storage Temperature ..............–55 °C to +150°C Recommended Operating Conditions (2) SP Supply Voltage (VSP).................. 7.5V to 24V Peak Output Current......................9A Maximum Operating Temperature .............–40 °C to +85°C Thermal Resistance (3) θJA θJC SOIC8N .................................. 50 ....... 8.... °C/W Notes: 1) Exceeding these ratings may damage the device. 2) The device is not guaranteed to function outside of its operating conditions. 3) Measured on approximately 1” square of 1 oz copper. ELECTRICAL CHARACTERISTICS VSP = 12V, VSHDN = 0V, TA = +25°C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units SP Operating Current 1.5 2.5 mA SP Shutdown Current VSHDN = 2V 2.5 10 µA SHDN, SP Threshold Low 1 V SHDN, SP Threshold High 2 V SHDN, SP Input Bias Current 1 µA SW On Resistance VSP = 7.5V, High-Side and Low-Side 0.1 Ω VPWM = 5, (Sinking) 9 A SW Current Limit (4) VPWM = 0, (Sourcing) 9 A SW Switching Frequency VPWM = 0 to 2V, 50% Duty Cycle 1.2 MHz SW Maximum Duty Cycle (5) VSP = 7.5V, VPWM = 2V, CSW 100nF, fSW = 3.3KHz 99.5 % SW Rise/Fall Time VPWM = 0 to 5V 20 ns PWM Pulse Width VPWM = 0 to 2V, High or Low Pulse 200 ns PWM to SW Delay Time Rising VPWM = 0 to 5V 70 ns PWM to SW Delay Time Falling VPWM = 5 to 0V 70 ns Thermal Shutdown Temperature (4) TJ Rising, Hysteresis = 20°C 160 °C Notes: 4) Guaranteed by design; not production tested. 5) SW drives low for 1.5µs every 300µs to charge the BS to SW capacitor. PWM SP SW GND FLT DRV SHDN BS 1 2 3 4 8 7 6 5 TOP VIEW MP8040_PD01-SOIC8N EXPOSED PAD ON BACKSIDE CONNECT TO PIN 4 |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |