Preliminary
2-229
RF2162
Rev A19 060208
Pin
Function
Description
Interface Schematic
1GND
Ground connection. Connect to package base ground. This ground
should be isolated from the backside ground contact on top metal layer.
2GND1
Ground for stage 1. Keep traces physically short and connect immedi-
ately to ground plane for best performance. This ground should be iso-
lated from the backside ground contact on top metal layer.
3GND1
Same as Pin 2.
4RF IN
RF input. An external DC blocking capacitor is required if this port is
connected to a DC path to ground or a DC voltage.
5VREG1
Enable voltage for first stage. When this pin is “low”, all circuits are shut
off. When this pin is 2.8V, all circuits are operating normally. VREG
requires a regulated 2.8V for the amplifier to operate properly over all
specified temperature and voltage ranges. A dropping resistor from a
higher regulated voltage may be used to provide the required 2.8V. A
100pF high frequency bypass capacitor is recommended.
6VMODE
This is an analog bias current control pin. The range is 0V for minimum
bias to 3.0 for maximum bias.
7VREG2
Enable voltage for second or output stage. When this pin is “low”, all cir-
cuits are shut off. When this pin is 2.8V, all circuits are operating nor-
mally. VREG requires a regulated 2.8V for the amplifier to operate
properly over all specified temperature and voltage ranges. A dropping
resistor from a higher regulated voltage may be used to provide the
required 2.8V. A 100pF high frequency bypass capacitor is recom-
mended.
8GND
Bias circuitry ground. See application schematic.
9GND
Ground connection. Connect to package base ground. This ground
should be isolated from the backside ground contact on top metal layer.
10
RF OUT
RF output and power supply for the output stage. The bias for the out-
put stage is provided through this pin and pin 13. An external matching
network is required to provide the optimum load impedance; see the
application schematics for details.
11
RF OUT
Same as pin 10.
See pin 10.
12
RF OUT
Same as pin 10.
13
2FO
Harmonic trap. This pin connects to the RF output but is used for pro-
viding a low impedance to the second harmonic of the operating fre-
quency. An inductor or transmission line resonating with an on chip
capacitor at 2fo is required at this pin.
14
VCC BIAS
Power supply for bias circuitry. A 100pF high frequency bypass capaci-
tor is recommended.
15
VCC1
Interstage tuning and bias supply for first stage.
16
VCC1
Interstage tuning and bias supply for first stage.
Pkg
Base
GND
Ground connection. The backside of the package should be soldered to
a top side ground pad which is connected to the ground plane with mul-
tiple vias. The pad should have a short thermal path to the ground
plane.
GND1
RF IN
VCC1
From Bias
Stages
RF OUT
From Bias
Stages
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