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Date: 6-28-04

SP706 +3.0/ +3.3 Low Power Microprocessor Circuits

© Copyright 2004 Sipex Corporation

To build an early-warning circuit for power

failure, connect the PFI pin to a voltage divider

as shown in Figure 16. Choose the voltage

divider ratio so that the voltage at PFI falls

below 1.25V just before the +5V regulator drops

out. Use PFO to interrupt the

µP so it can prepare

for an orderly power-down.

Manual Reset

The manual-reset input (MR) allows RESET to

be triggered by a pushbutton switch. The switch

is effectively debounced by the 140ms

minimum RESET pulse width. MR is TTL/

CMOS logic compatible, so it can be driven by

an external logic line. MR can be used to force

a watchdog timeout to generate a RESET pulse

in the SP706P/R/S/T-SP708R/S/T series.

Simply connect WDO to MR.

Figure 14. Watchdog Timing Waveforms

Figure 15. Timing Diagrams with WDI Tri-stated. The RESET Output is the Inverse of the RESET Waveform

Shown.

RESET*

WDO

0V

WDI

RESET*

0V

+3.3V

0V

0V

* externally triggered LOW by MR,

RESET is for the SP813L/813M only

+3.3V

+3.3V

+3.3V

RESET

0V

0V

0V

0V

MR*

WDO

*externally driven LOW

+3.3V

+3.3V

+3.3V

+3.3V