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Date: 4/18/05

SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation

10k

Ω and the output saturation voltage is below

0.4V while sinking 40

µA. When using a 10kΩ

external pull-down resistor, the high state for

the RESET output with Vcc = 4.75V is 4.5V

typical. For battery voltages less than or equal

RESET and RESET are asserted when V

below the reset threshold and remain asserted

for the Reset Timeout Period (200ms nominal)

after V

on power-up. Refer to Figure 19. The devices'

battery-switchover comparator does not affect

reset assertion. However, both reset outputs are

asserted in battery-backup mode since V

be below the reset threshold to enter this mode.

Figure 18. External Pull-down Resistor Ensures

RESET is Valid with V

TO µP RESET

10kΩ

15

Corporation

RESET

Figure 19. Reset and Chip-Enable Timing

4) Watchdog function ➡ Monitors

µP activity

where the watchdog output goes to a logic

LOW state if the watchdog input is not

toggled for greater than the timeout period.

5) Internal switch ➡ Switches over from V

CC

to V

threshold.

RESET and RESET Outputs

The SP691A/693A/800L/800M devices'

RESET and RESET outputs ensure that the

µP

powers up in a known state, and prevents

code-execution errors during power-down or

brownout conditions.

The RESET output is active low, and typically

sinks 3.2mA at 0.1V saturation voltage in its

active state. When deasserted, RESET sources

is open drain, active high, and typically sinks

3.2mA with a saturation voltage of 0.1V. When

no backup battery is used, RESET output is

an external 10k

Ω pull-down resistor on RESET

goes below 1V, the gate drive to the RESET

output switch reduces accordingly, increasing

the R

10k

Ω pull-down resistor ensures the parallel

combination of switch plus resistor is around

Vcc

RESET

12µ

100µs

100µs

RESET

THRESHOLD

RESET