SP3203ECYSLASHTR datasheet(9/16 Pages) SIPEX

9 / 16 page

Date: 03/01/05

SP3203E, 3V RS232 Serial Transceiver with Logic Selector and 15kV ESD

consists of a regulated dual charge pump that

provides output voltages of 5.5V regardless of

the input voltage (VCC) over the +3.0V to +5.5V

range. This is important to maintain compliant

RS-232 levels regardless of power supply

fluctuations.

The charge pump operates in a discontinuous

mode using an internal oscillator. If the output

voltages are less than a of 5.5V, the charge

pump is enabled. If the output voltages exceed

a of 5.5V, the charge pump is disabled. This

oscillator controls the four phases of the voltage

shifting (Figure 12). A description of each phase

follows.

VSS Charge Storage-Phase 1(Figure 13)

During this phase of the clock cycle, the positive

side of capacitors C1 and C2 are initially charged

to VCC. Cl+ is then switched to GND and the

charge in C1– is transferred to C2–. Since C2+ is

connected to VCC, the voltage potential across

capacitor C2 is now 2 times VCC.

Table 1. SHUTDOWN Truth Table.

(Note: When device in shutdown, the SP3203E's charge pump is turned off

and V+ decays to V

CC. V- is pulled to ground and the transmitter outputs

are disabled as High Impendance).

Figure 9. Loopback Test Circuit for RS-232 Driver Data

Transmission Rates

VSS Transfer-Phase 2 (Figure 14)

Phase two of the clock connects the negative

terminal of C2 to the VSS storage capacitor and

the positive terminal of C2 to GND. This

transfers a negative generated voltage to C3.

This generated voltage is

regulated to a minimum voltage of -5.5V.

Simultaneous with the transfer of the voltage

to C3, the positive side of capacitor C1 is

switched to VCC and the negative side is

connected to GND.

VDD Charge Storage-Phase 3 (Figure 15)

The third phase of the clock is identical to the

first phase — the charge transferred in C1 pro-

Figure 10. Loopback Test Circuit Result at 120Kbps

(All Drivers Fully Loaded)

Figure 11. Loopback Test Circuit result at 250Kbps

(All Drivers Fully Loaded)

SP3203E

GND

1IN

XIN

C1+

C1-

C2+

C2-

V+

V-

VCC

0.1µF

TTL/CMOS

INPUTS

+3V to +5V

SHUTDOWN

5KΩ

1OUT

5KΩ

XIN

XOUT

TTL/CMOS

OUTPUTS

1IN

XOUT

1OUT

VCC

1000pF

V L

+3V to +5.5V

Ch1

Ch3

[]

T1 IN

T1 OUT

R1 OUT

5.00V

Ch2 5.00V M 5.00µs Ch1

5.00V

[]

T1 IN

T1 OUT

R1 OUT

Ch1

Ch3

5.00V

Ch2 5.00V M 2.50µs Ch1

5.00V

SP3203ECY/TR 数据表(PDF) 9 Page - Sipex Corporation

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