5-38
RF2483
Rev A8 060203
Pin
Function
Description
Interface Schematic
1VCC3
Supply for RF output circuits.
2VCC2
Supply for modulator and biasing circuits.
3ISIG P
In phase I channel positive baseband input port. Best performance is
achieved when the ISIGP and ISIGN are driven differentially. The rec-
ommended CW differential drive level (VISIGP-VISIGN) is 800mVP-P.
This input should be DC-biased at 1.2V±0.05V. The common-mode
DC coltage on the ISIGP and ISIGN input signals is used to bias the
modulator. In sleep mode an internal FET switch is opened, the input
goes high impedance and the modulator is de-biased. The input imped-
ance is typically 5.5k
Ω at low frequencies and at higher frequencies
can be modeled as 50
Ω in series with 12pF to ground.
Phase or amplitude errors between the ISIGP and ISIGN signals may
result in the even order distortion of the modulation in the output spec-
trum.
DC offsets between the ISIGP and ISIGN signals will result in
increased carrier leakage. Small DC offsets may be deliberately
applied between the ISIGP/ISIGN and QSIGP/QSIGN inputs to cancel
out LO leakage. The optimum corrective DC offsets will change with
mode, frequency and gain control.
Common-mode noise on the ISIGP and ISGN should be kept low as it
may degrade the noise performance of the modulator.
Phase offsets may be applied between the I and Q channels to improve
the sideband suppression performance.
4ISIG N
In phase I channel negative baseband input port. See ISIGP.
5
ENABLE
Enables power to the device.
CMOS input.
Logic 1 (1.4V to VCC)=Enabled.
Logic 0 (0V to 0.5V)=Powered Down.
6VCC1
Supply for the LO buffers and quadrature network.
The sideband suppression is a function of the VCC1 voltage. The inclu-
sion of R3 (39
Ω) lowers the voltage on VCC1 by around 400mV and
results an improvement in sideband suppression but around a 0.2dB
increase in noise at 20MHz offset.
VCC3
RF Output
Amplifier
VCC2
Modulator and
VGA
VCC2
V
CC2
12 pF
50
Ω
V
CC2
12 pF
50
Ω
V
CC2
VCC1
LO Quadrature
Generator and
Buffers
GND1
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