Date: 4/18/05

SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation

18

PFI

PFO

+5V

GND

PFO

V-

+5V

0V

V-

5.0 - 1.25

=

Figure 28. Monitoring a Negative Voltage

Negative-Going V

While asserting resets to the

µP during power-up,

power-down, and brownout conditions, these

supervisors are relatively immune to short-

usually undesirable to reset the

experiences only small glitches.

Refer to Figure 29 for a graph of the maximum

transient duration vs. the reset-comparator over-

drive for which reset pulses are not generated.

The graph was produced using negative-going

pulses, starting at 5V and ending below the

reset threshold by the magnitude indicated

(reset comparator overdrive). The graph shows

transient may typically have without causing a

reset pulse to be issued.

As the amplitude of the transient increases

(i.e., goes farther below the reset threshold), the

maximum allowable pulse width decreases.

below the reset threshold and lasts for 40

µs or

less will not cause a reset pulse to be issued.

A 100nF bypass capacitor mounted close to the

Connecting a Timing Capacitor to OSC

IN

When OSC

disconnects from its internal 10

µA pull-up and

is internally connected to a +100nA current

source. When a capacitor is connected from

OSC

watchdog timeout period), the current source

charges and discharges the timing capacitor to

create the oscillator that controls the reset and

watchdog timeout period. To prevent timing

errors, minimize external current leakage

sources at this pin, and locate the capacitor as

close to OSC

board leakage plus the OSC capacitor leakage

must be small compared to +100nA.

Figure 29. Maximum Transient Duration Without

Causing a Reset Pulse vs. Reset Comparator Overdrive

Reset Comparator Overdrive

(Reset Threshold Voltage - V

1

10

1000

10000

160

120

80

40

0

0.1µF Capacitor

V

Above Line

Reset Generated