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5-133
RF2705G
Rev A0 060206
Evaluation Board Schematic
7
6
5
4
3
2
1
12
11
10
9
8
18
17
16
15
14
13
23
22
21
20
19
24
Note: The die flag is the
chip's main ground.
+45°
-45°
Σ
DIV
2
+45°
-45°
Flo
x2
Mode Control
and Biasing
Power
Control
C6
5.6 pF
MODE B
MODE A
C1
1 nF
VCC
50
Ωμstrip
J1
I SIG N
50
Ωμstrip
J2
I SIG P
C4
1.8 pF
L1
3.9 nH
50
Ωμstrip
J3
HB LO
C13
3 pF
L6
22 nH
50
Ωμstrip
J6
LB LO
MODE C
MODE D
50
Ωμstrip
J8
Q SIG N
50
Ωμstrip
J9
Q SIG P
C15
1 nF
C14
10 nF
P1
1
2
3
4
CON4
P2-1
MODE D
P2-4
MODE A
P2-3
MODE B
P2-2
MODE C
GC
L7
12 nH
C17
3.3 pF
R4
1 k
Ω
L8
12 nH
C16
3.3 pF
C8
100 pF
C18
0.5 pF
VCC
50
Ωμstrip
J7
LB RF OUT
L4
4.3 nH
C9
1.6 pF
R3
430
Ω
L5
4.3 nH
C10
1.6 pF
C11
22 pF
C5
DNI
VCC
50
Ωμstrip
J5
HB RF OUT
L2
2.2 nH
C2
4.3 pF
R1
1 k
Ω
L3
2.2 nH
C3
4.3 pF
C7
12 pF
C12
1.3 pF
VCC
50
Ωμstrip
J4
WB RF OUT
T2
Murata
LDB211G8020C-001
T1
Murata
LDB211G9020C-001
T3
Murata
LDB21906M20C-001
R2
430
Ω
GND
VCC
P1-1
GC
P1-3
P2
1
2
3
CON3