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SP6136EB 数据表(PDF) 6 Page - Sipex Corporation |
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SP6136EB 数据表(HTML) 6 Page - Sipex Corporation |
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6 / 9 page ![]() Rev 5/01/06 SP6136 Evaluation Manual Copyright © 2006 Sipex Corporation Page 6 of 9 The simple guidelines for positioning the poles and zeros and for calculating the component values for Type III compensation are as follows: K R 1 . 68 1 = 8 . 0 1 8 . 0 2 − × = Vout R R (sets output voltage) LC R ZSF CZ 1 1 1 3 × × = (sets first zero) ( ) ( ) Vin Vramp CZ fc Cout L fc RZ × × × + × × × = 3 28 . 6 1 28 . 6 2 2 (sets the cross-over frequency, fc) LC RZ ZSF CZ 1 2 1 2 × × = (sets second zero) 2 28 . 6 1 1 RZ fs CP × × = (sets first high-frequency pole) 3 28 . 6 1 3 CZ fs RZ × × = (sets second high-frequency pole) Where ZSF=(f compensation double zero)/(f circuit double pole) Here ZSF is set at 0.8. As a particular example, consider for the following SP6136EB, 7AMAX with a type III Voltage Loop Compensation component selections: Vin = 12V Vout = 3.30V @ 0 to 7A load Select L = 2.2 uH => 30% current ripple. Select Cout = 100uF Ceramic capacitor (Resr ≈ 5mΩ) fs = 600KHz SP6136ER1 internal Oscillator Frequency Vramp_pp = 1.0V SP6136ER1 internal Ramp Peak to Peak Amplitude |
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