5

(SRz2Cz2+1)(SR1Cz

3+1)

SR1Cz2(SRz3Cz3+1)(SRz2C

1+1)

Vin

Vramp_p

(SResrCout+

1)

[S^2LCout+S(Resr+Rdc)Co

t+1]

(R1+R2

)

R2

OR

Vout

Vref

Vout

(Volts

)

Vref

(Volts

)

Type III Voltage

L

(Volts

)

Vfbk

Gout(S)

Gain Block

Compensation Gamp(S)

PWM Stage

Output Stage

Gain Block

Gain Block

Gpwm

Gain Block

Gfbk

Voltage Feedback

Resr

:= Output Capacitor Equivalent Series Resitance

Definition

Rdc

:= Output Inductor DC Resistance

Vramp_pp := SP7655 Internal RAMP Amplitude Peak to Peak Voltage

Output Load Resistance >> Resr and Rdc

Cz2 >> Cp1 and R1 >> Rz3

Condition

Figure 11. Voltage Mode Control Loop with Loop Dynamic for Type III Compensation