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TMP112BIDRLR 数据表(PDF) 22 Page - Texas Instruments

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部件名 TMP112BIDRLR
功能描述  TMP112x High-Accuracy, Low-Power, Digital Temperature Sensors With SMBus and Two-Wire Serial Interface in SOT563 and X2SON Packages
PDF  41 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TMP112BIDRLR 数据表(HTML) 22 Page - Texas Instruments

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7.4.4 Thermostat Mode (TM)
The thermostat mode bit indicates to the device whether to operate in comparator mode (TM = 0 ) or interrupt
mode (TM = 1).
7.4.4.1 Comparator Mode (TM = 0)
In Comparator mode (TM = 0), the Alert pin and status flag are activated when the temperature equals or
exceeds the value in the T(HIGH) register and remains active until the temperature falls below the value in the
T(LOW) register. For more information on the comparator mode, see the Section 7.5.4.
7.4.4.2 Interrupt Mode (TM = 1)
In Interrupt mode (TM = 1), the Alert pin is activated with the conditions explained in the Section 7.5.4. The
Alert pin is cleared when the host controller reads the temperature register. For more information on the interrupt
mode, see the Section 7.5.4.
7.5 Programming
7.5.1 Pointer Register
Figure 7-8 shows the internal register structure of the TMP112 family. The 8-bit Pointer Register of the device is
used to address a given data register. The Pointer Register uses the two LSBs (see Table 7-13) to identify which
of the data registers must respond to a read or write command. The power-up reset value of P1/P0 is '00'. By
default, the TMP112 family reads the temperature on power-up.
I/O
Control
Interface
SCL
SDA
Temperature
Register
Configuration
Register
T
LOW
Register
T
HIGH
Register
Pointer
Register
Figure 7-8. Internal Register Structure
Table 7-6 lists the pointer address of the registers available in the TMP112 family. Table 7-7 lists the bits of the
Pointer Register byte. During a write command, bytes P2 through P7 must always be 0.
Table 7-6. Pointer Addresses
P1
P0
REGISTER
0
0
Temperature Register (Read Only)
0
1
Configuration Register (Read/Write)
1
0
TLOW Register (Read/Write)
1
1
THIGH Register (Read/Write)
TMP112, TMP112D
SBOS473L – MARCH 2009 – REVISED JULY 2024
www.ti.com
22
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Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: TMP112 TMP112D



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