SC28L198 datasheet(22/56 Pages) PHILIPS

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Philips Semiconductors

Product specification

SC28L198

Octal UART for 3.3V and 5V supply voltage

1999 Jan 14

Table 8. CR – Command Register

CR is used to write commands to the Octal UART.

Bits 7:3

Bit 2

Bit 1

Bit 0

Channel Com-

mand codes

see “Command

Lock TxD and

RxFIFO en-

ables

Enable Tx

Enable Rx

CR[2] – Lock TxD and RxFIFO enables

If set, the transmitter and receiver enable bits, CR[1:0] are not

significant. The enabled/disabled state of a receiver or transmitter

can be changed only if this bit is at zero during the time of the write

to the command register. WRITES TO THE UPPER BITS OF THE

CR WOULD USUALLY HAVE CR[2] AT 1 to maintain the condition

of the receiver and transmitter. The bit provides a mechanism for

writing commands to a channel, via CR[7:3], without the necessity of

keeping track of or reading the current enable status of the receiver

and transmitter.

CR[1] – Enable Transmitter

A one written to this bit enables operation of the transmitter. The

TxRDY status bit will be asserted. When disabled by writing a zero

to this bit, the command terminates transmitter operation and resets

the TxRDY and TxEMT status bits. However, if a character is being

transmitted or if characters are loaded in the TxFIFO when the

transmitter is disabled, the transmission of the all character(s) is

completed before assuming the inactive state.

CR[0] – Enable Receiver

A one written to this bit enables operation of the receiver. If not in

the special wake up mode, this also forces the receiver into the

search for start bit state. If a zero is written, this command

terminates operation of the receiver immediately – a character being

received will be lost. The command has no effect on the receiver

status bits or any other control registers. If the special wake–up

mode is programmed, the receiver operates even if it is disabled

(see Wake–up Mode).

CR[7:3] – Miscellaneous Commands ( See Table below)

The encoded value of this field can be used to specify a single

command as follows:

00000

No command.

00001

Reserved

00010

Reset receiver. Resets the receiver as if a hardware reset

had been applied. The receiver is disabled and the FIFO

pointer is reset to the first location effectively discarding all

unread characters in the FIFO.

00011

Reset transmitter. Resets the transmitter as if a hardware

reset had been applied.

00100

Reset error status. Clears the received break, parity error,

framing error, and overrun error bits in the status register

(SR[7:4]). Used in character mode to clear overrun error

status (although RB, PE and FE bits will also be cleared),

and in block mode to clear all error status after a block of

data has been received.

00101

Reset break change interrupt. Causes the break detect

change bit in the interrupt status register (ISR[2]) to be

cleared to zero.

00110

Start break. Forces the TxD output low (spacing). If the

transmitter is empty, the start of the break condition will be

delayed up to two bit times. If the transmitter is active, the

break begins when transmission of the current character

is completed. If there are characters in the TxFIFO, the

start of break is delayed until those characters, or any

others loaded after it have been transmitted (TxEMT must

be true before break begins). The transmitter must be

enabled to start a break.

00111

Stop break. The TxD line will go high (marking) within two

bit times. TxD will remain high for one bit time before the

next character, if any, is transmitted.

01000

Assert RTSN. Causes the RTSN output to be asserted

(low).

01001

Negate RTSN. Causes the RTSN output to be negated

(high).

Note: The two commands above actually reset and

set, respectively, the I/O2 or I/O1 pin associated with

the I/OPIOR register.

01010

Reserved

01011

Reserved

01100

Reserved

01101

Block error status mode. Upon reset of the device or an

individual receiver, the block mode of receiver error status

accumulates as each character moves to the bottom of

the RxFIFO, the position from which it will be read. In this

mode of operation, the RxFIFO may contain a character

with non–zero error status for some time. The status will

not reflect the error character’s presence until it is ready to

be popped from the RxFIFO. Command 01101 allows the

error status to be updated as each character is pushed

into the RxFIFO. This allows the earliest detection of a

problem character, but complicates the determination of

exactly which character is causing the error. This mode of

block error accumulation may be exited only by resetting

the chip or the individual receiver.

01111

Reserved.

10000

Transmit an Xon Character

10001

Transmit an Xoff Character

10010

Reserved for channels b–h, for channel a: enables a

Gang Write of Xon Character Registers. After this

command is issued, a write to the channel A Xon

Character Register will result in a write to all channel’s

Xon character registers. This command provides a

mechanism to initialize all the Xon Character registers

with one write. A write to channel A Xon Character

write mode.

10011

Reserved for channels b–h, for channel a: enables Gang

Write of Xoff Character Registers. After this command is

issued, a write to the channel A Xoff Character Register

will result in a write to all channel’s Xoff character

registers. This command provides a mechanism to

initialize all the Xoff Character registers with one write. A

write to channel A Xoff Character Register returns the

Octal UART to the individual Xoff write mode.

Note: Gang writing of Xon/Xoff Character Commands: Issuing

command causes the next write to Xon/Xoff Character Register

A to effect a simultaneous write into the other 3 Xon/Xoff

character registers. After the Xon/Xoff Character Register A is

written, the 28L198 returns to individual write mode for the

Xon/Xoff Character Registers. Other intervening reads and

writes are ignored. The device resets to individual write mode.

10100 Reserved for channels b-h, for channel a: executes a Gang

Load of Xon Character Registers. Executing this

command causes a write of the value x’11 to all channel’s

Xon character registers. This command provides a

mechanism to initialize all the Xon Character registers to a

default value with one write. Execution of this command

is immediate and does not effect the timing of subsequent

host I/O operations.

10101

Reserved for channels b-h, for channel a: executes a

Gang Load of Xoff Character Registers. Executing this

command causes a write of the value x’13 to all channel’s

Xoff character registers. This command provides a

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