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PL611S-02-XXXGC-R 数据表(PDF) 1 Page - PhaseLink Corporation |
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PL611S-02-XXXGC-R 数据表(HTML) 1 Page - PhaseLink Corporation |
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1 / 8 page ![]() (Preliminary)PL611s-02 1.8V-3.3V PicoPLL TM, World’s Smallest Programmable Clock 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 1 1 2 3 4 5 6 OE, PDB, FSEL, CLK1 GND XIN/FIN VDD XOUT CLK0 DFN DFN DFN DFN----6 6 6 6L L L L (2.0mmx1.3mmx0.6mm) SOT SOT SOT SOT23 23 23 23----6 6 6 6L L L L (3.0mmx3.0mmx1.35mm) 1 2 3 4 5 6 XOUT GND XIN/FIN VDD SC SC SC SC70 70 70 70----6 6 6 6L L L L (2.3mmx2.25mmx1.0mm) CLK0 OE, PDB, FSEL, CLK1 XIN/FIN GND XOUT VDD CLK0 1 2 3 OE, PDB, FSEL, CLK1 6 5 4 FEATURES • Lowest-power, smallest Programmable PLL • Very low Jitter and Phase Noise • Output Frequency up to: o 133MHz @ 1.8V operation o 166MHz @ 2.5V operation o 200MHz @ 3.3V operation • Input Frequency: o Fundamental Crystal: 10MHz to 50MHz o Reference Clock: 1MHz to 200MHz • Accepts >0.1V reference signal input voltage • One I/O pin can be configured as Output Enable (OE), Frequency switching (FSEL), Power Down (PDB) input, or CLK1 output. • <10 A current consumption with PDB active. • Single 1.8V, 2.5V, or 3.3V ± 10% power supply • Operating temperature range from -40°C to 85°C • Available in 6-pin DFN, SOT23, and SC70 GREEN/RoHS compliant packages. DESCRIPTION The PL611s-02 is a low-power, small form factor, high performance OTP-base programmable frequency synthesizer and a member of PhaseLink’s PicoPLL Factory Programmable ‘Quick Turn Clocks. Designed to fit in a small DFN, SC70, or SOT23 package for a broad range of applications, the PL611s-02 offers the best phase noise and jitter performance, and power consumption of its rivals. . In addition, one programmable I/O pin can be configured as Output Enable (OE), Frequency switching (FSEL), Power Down (PDB) input, or CLK1 (FOUT, FREF, FREF/2) output. The power down feature of PL611s-02, when activated, allows the IC to consume less than 10 A of power, while its programming flexibility allows generating any output, up to 200MHz using a low-cost crystal or reference input. PACKAGE PIN CONFIGURATION BLOCK DIAGRAM Phase Detector Charge Pump Loop Filter VCO XIN/FIN XOUT R-Counter (8-bit) FVCO = FREF * (2 * M/R) FOUT = FVCO / (2 * P) CLK0 FREF Programming Logic OE, PDB, FSEL, CLK1 XTAL OSC M-Counter (11-bit) P-Counter (5-bit) Programmable CLoad Programmable Function |
类似零件编号 - PL611S-02-XXXGC-R |
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类似说明 - PL611S-02-XXXGC-R |
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