(Preliminary)

PL611s-15

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 07/18/06 Page 2

PACKAGE PIN ASSIGNMENT

Pin #

Name

SOT

SC70

DFN

Type

Description

VDD

1

3

3

P

VDD connection.

GNDA

2

2

2

P

Ground connection for Analog Circuitry.

FIN

3

1

1

I

Reference input pin.

LF

4

6

6

I

Loop Filter input pin.

GND

5

5

5

P

GND connection

CLK0

6

4

4

O

Programmable Clock Output

GUIDELINES FOR EXTERNAL COMPONENT SELECTION

For the optimum performance, accurate external loop filter components must be selected. A general guideline for

selecting these components based on the input frequency is shown in the below table. Please contact PhaseLink

for more accurate component selections.

Input frequency

Capacitor Value

Resistor Value

3MHz ~ 200MHz

4.7nF

2.2KΩ

300KHz ~ 10MHz

4.7nF

6.8KΩ

30KHz ~ 1.0MHz

4.7nF

22KΩ

10KHz ~ 100KHz

47nF

22KΩ

APPLICATION RECOMMENDATIONS FOR PL611s-15

PL611s-15 can accept a reference input >10KHz and produce a clock output in the MHz range, as shown in the

diagram ‘1’, below. However, to save costs in consumer product system designs and for greater area optimization,

it is possible to use the XOUT of the RTC crystal (32.768KHz) as the reference input to the PL611s-15, as shown

in diagram ‘2’, below.

Diagram ‘1’

Diagram ‘2’

Note: An AC Coupling Cap may be required if RTC Clock amplitude is too small.

32.768K

Hz

C1

C2

REFIN

MHZ CLK

(Any Frequency)

1.8~3.3V

LF

LPGND

ASIC

XIN

XOUT

XIN

XOUT

REFIN

MHZ CLK

(Any Frequency

1.8~3.3V

LF

LPGND