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PL611S-18-XXXTC-R 数据表(PDF) 1 Page - PhaseLink Corporation |
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PL611S-18-XXXTC-R 数据表(HTML) 1 Page - PhaseLink Corporation |
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1 / 9 page ![]() (Preliminary)PL611s-18 0.5kHz-125MHz MHz to KHz Programmable Clock T M 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/23/07 Page 1 FEATURES • Designed for Very Low-Power applications • Offered in Tiny GREEN/RoHS compliant packages o 6-pin DFN (2.0mmx1.3mmx0.6mm) o 6-pin SC70 (2.3mmx2.25mmx1.0mm) o 6-pin SOT23 (3.0mmx3.0mmx1.35mm) • Accepts Crystal or Reference Clock inputs • Input Frequency: o Fundamental crystal: 10MHz to 50MHz o Reference Input: 1MHz to 125MHz • Accepts >0.1V reference signal input voltage • Output Frequency 0.5kHz to 125MHz CMOS. o 65MHz @ 1.8V operation o 90MHz @ 2.5V operation o 125MHz @ 3.3V operation • One programmable I/O pin can be configured as OE, PDB, FSEL or CLK1 • Low current consumption: o <1.0mA with 27MHz & 32kHz outputs o < 5 A when PDB is activated • Single 1.8V, 2.5V, or 3.3V ± 10% power supply • Operating temperature range from -40°C to 85°C DESCRIPTION The PL611s-18 is a low-cost general purpose frequency synthesizer and a member of PhaseLink’s PicoPLL family, the worlds smallest programmable clocks. PhaseLink’s PL611s-18 offers the versatility of using a single Crystal (MHz) or Reference Clock input and producing up to two (kHz/MHz) system clocks, or a combination of Reference and low frequency outputs. The PL611s-18 is designed for low-power applications with very stringent space requirements and consumes ~1.0mA, while producing 2 distinct outputs of 27MHz and 32kHz. The power down feature of PL611s-18, when activated, allows the IC to consume less than 5 A of power. The PL611s-18 fits in a small DFN, SC70, or SOT23 package. Cascading of the PL611s-18 with other PhaseLink programmable clocks allow generating system level clocking requirements, thereby reducing the overall system implementation cost. In addition, one programmable I/O pin can be configured as Output Enable (OE), Frequency switching (FSEL), Power Down (PDB) input, or CLK1 (CLK0, FREF, FREF/2) output. BLOCK DIAGRAM Phase Detector Charge Pump Loop Filter VCO XIN/FIN XOUT R-Counter (5-bit) FVCO = FREF * (2 * M/R) FOUT = FVCO / (2 * P) CLK FREF Programming Logic OE, PDB, FSEL, CLK1 XTAL OSC M-Counter (8-bit) P-Counter (14-bit) Programmable CLoad Programmable Function |
类似零件编号 - PL611S-18-XXXTC-R |
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类似说明 - PL611S-18-XXXTC-R |
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