1.8V-3.3V PicoPLL

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 2

KEY PROGRAMMING PARAMETERS

CLK

Output Frequency

Output Drive Strength

Programmable

Input/Output

Where M = 11 bit

R = 8 bit

P = 5 bit

Three optional drive strengths to

choose from:

• Low: 4mA

• Std: 8mA (default)

• High: 16mA

One output pin can be configured

as:

• OE - input

• PDB - input

• CLK1 – output

PACKAGE PIN CONFIGURATION AND DESCRIPTION

PIN DESCRIPTION

Pin Assignment

Name

DFN Pin#

SOT Pin #

Type

Description

OE,

PDB,

CLK1

2

1

I/O

This programmable I/O pin can be configured as an Output Enable (OE)

input, Power Down input (PDB) or CLK1 Clock output. This pin has an

internal 60K

pull up resistor (OE and PDB functions only).

Pin State

OE

PDB

0

Disable CLK

Power Down Mode

1 (default)

Normal mode

Normal mode

GND

3

2

P

GND connection

FIN

1

3

I

Reference input pin

FSEL

6

4

I

Frequency Switching Input pin. This pin has an internal 60K

pull up

resistor.

FSEL

State

0

Frequency 2

1 (default)

Frequency 1

VDD

5

5

P

VDD connection

CLK0

4

6

O

Programmable Clock Output

1

2

3

4

5

6

OE, PDB, CLK1

GND

FIN

VDD

FSEL

CLK0

SOT

SOT

SOT

SOT23

23

23

23----6

6

6

6L

L

L

L

((((3

3

3

3....0

0

0

0mmx

mmx

mmx

mmx3

3

3

3....0

0

0

0mmx

mmx

mmx

mmx1

1

1

1....35

35

35

35mm

mm

mm

mm))))

DFN

DFN

DFN

DFN----6

6

6

6L

L

L

L

((((2

2

2

2....0

0

0

0mmx

mmx

mmx

mmx1

1

1

1....3

3

3

3mmx

mmx

mmx

mmx0

0

0

0....6

6

6

6mm

mm

mm

mm))))

FIN

GND

FSEL

VDD

CLK0

1

2

3

OE,PDB,CLK1

6

5

4