1.8V-3.3V PicoPLL

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 3/9/07 Page 2

KEY PROGRAMMING PARAMETERS

CLK[0:1]

Output Frequency

Output Drive Strength

Programmable

Input/Output

Where M = 11 bit

R = 8 bit

P = 5 bit

Three optional drive strengths to

choose from:

• Low: 4mA

• Std: 8mA (default)

• High: 16mA

One output pin can be configured

as:

• OE - input

• PDB - input

• FSEL – input

PACKAGE PIN ASSIGNMENT

Pin Assignment

Name

SOT

Pin #

SC70

Pin#

DFN

Pin#

Type

Description

OE, PDB,

FSEL, CLK1

1

2

2

I/O

This programmable I/O pin can be configured as an Output Enable

(OE) input, Power Down (PDB) input, On-the-Fly Frequency Switching

Selector (FSEL)input or CLK1 clock output. This pin has an internal

60K

pull up resistor (OE, PDB & FSEL Only).

The OE and PDB features can be programmed to allow the output to

float (Hi Z), or to operate in the ‘Active low’ mode.

State

OE

PDB

FSEL

0

Disable CLK

Power Down Mode

Frequency ‘2’

1 (default)

Normal mode

Normal mode

Frequency ‘1’

GND

2

1

3

P

GND connection

XIN, FIN

3

3

1

I

Crystal or Reference input pin

Crystal Output pin

XOUT

4

4

6

O

Do Not Connect (DNC ) when FIN is present

VDD

5

5

5

P

VDD connection

CLK0

6

6

4

O

Programmable Clock Output