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PLL103-02XC-R 数据表(PDF) 1 Page - PhaseLink Corporation |
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PLL103-02XC-R 数据表(HTML) 1 Page - PhaseLink Corporation |
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1 / 6 page ![]() PLL103-02 DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1 FEATURES • Generates 24 output buffers from one input. • Supports up to four DDR DIMMS. • Supports 266MHz DDR SDRAM. • One additional output for feedback. • Less than 5ns delay. • Skew between any outputs is less than 100 ps. • 2.5V Supply range. • Enhanced DDR Output Drive selected by I2C. • Available in 48 pin SSOP. BLOCK DIAGRAM PIN CONFIGURATION Note: #: Active Low DESCRIPTION The PLL103-02 is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 can be used in conjunction with a clock synthesizer for the VIA Pro 266 chipset. The PLL103-02 also has an I2C interface, which can enable or disable each output clock. When powered up, all output clocks are enabled (have internal pull ups). DDR5C DDR4C DDR4T GND VDD2.5 DDR3C DDR3T GND VDD2.5 DDR2C GND VDD2.5 DDR1C DDR0C DDR0T GND VDD2.5 FBOUT SDATA VDD2.5 DDR5T DDR2T DDR10C VDD2.5 GND DDR9T DDR9C VDD2.5 PD# GND DDR8T DDR8C VDD2.5 N/C VDD2.5 GND DDR11T DDR11C DDR10T GND DDR6T DDR7T DDR7C GND SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 41 42 44 43 45 46 47 48 BUF_IN DDR1T DDR6C BUF_IN SDATA SCLK I2C Control PD# DDR0T DDR0C DDR1T DDR1C DDR2T DDR2C DDR3T DDR3C DDR4T DDR4C DDR5T DDR5C DDR6T DDR6C DDR7T DDR7C DDR8T DDR8C DDR9T DDR9C DDR10T DDR10C DDR11T DDR11C |
类似零件编号 - PLL103-02XC-R |
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类似说明 - PLL103-02XC-R |
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