PLL520-05/-06/-07/-08/-09

Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 2

PIN DESCRIPTIONS

Name

TSSOP*

Pin number

3x3mm QFN*

Pin number

Type

Description

XIN

2

13

I

Crystal in connector.

XOUT

3

14

I

Crystal out connector.

OE

6

16

I

Output enable pin.

VCON

7

1

I

Frequency control input (0.3V to 3.0V)

GND

8,9, 10, 14

2,3,4,8,12

P

Ground (except pin 12 on PLL520-06: DRIVSEL see below).

DRIVSEL**

-

12

I

PLL520-06 only: Drive Select Input. This pin has an internal

pull-up that will default DRIVSEL to ‘1’ when not connect to

GND. CMOS output of PLL520-06 will be high drive CMOS

when DRIVSEL is set to ‘0’, and will be standard CMOS

otherwise.

CLKT

11

5

O

True output PECL (PLL520-08) or LVDS (PLL520-09)

(N/C for PLL520-07)

CLKC

13

7

O

Complementary output PECL (PLL520-08) or LVDS

(PLL520-09)

(CMOS out for PLL520-07).

SEL0

16

10

I

SEL1

15

9

I

SEL2

5

15

I

SEL3

4

Not available

I

Multiplier selector pins. These pins have an internal pull-up

that will default SEL to ‘1’ when not connected to GND.

VDD

1, 12

6,11

P

+3.3V power supply.

* Note: PLL520-06 only available in 3x3mm QFN, PLL520-07 only available in TSSOP.

** Note: DRIVSEL on pin 12 on PLL520-06 only.

FREQUENCY SELECTION TABLE

SEL3*

SEL2

SEL1

SEL0

Selected Multiplier

0*

0

1

1

Fin x 8 (PLL520-09 in TSSOP only)

1*

0

1

1

Fin x 4

1*

1

1

0

Fin x 2

1*

1

1

1

No multiplication

Note *: SEL3 is not available (always “1”) in 3x3mm package

All pins have internal pull-ups (default value is 1). Connect to GND to set to 0.