PLL602-03

Low Phase Noise CMOS XO (48MHz to 100MHz)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1

FEATURES

• Low phase noise XO output for the 48MHz to

100MHz range (-130 dBc at 10kHz offset).

• 12 to 25MHz crystal input.

• Integrated crystal load capacitor: no external

load capacitor required.

• Low jitter (RMS): 3ps period jitter (1 sigma).

• Selectable High Drive (30mA) or Standard Drive

(10mA) output.

• 3.3V operation.

• Available in 8-Pin TSSOP or SOIC.

DESCRIPTION

The PLL602-03 is a low cost, high performance and

low phase noise XO, providing less than -130dBc at

10kHz offset in the 48MHz to 100MHz operating

range. The very low jitter (3ps RMS period jitter)

makes this chip ideal for applications requiring clean

reference frequency sources. Input crystal can range

from 12 to 25MHz (fundamental resonant mode).

PIN CONFIGURATION

OUTPUT RANGE

MULTIPLIER

FREQUENCY

RANGE

OUTPUT

BUFFER

X4

48 - 100MHz

CMOS

BLOCK DIAGRAM

Reference

Divider

Phase

Comparator

Charge

Pump

Loop

Filter

VCO

VCO

Divider

XTAL

OSC

OE

XIN

XOUT

CLK

1

2

3

45

6

7

8

CLK

VDD

OE^

XIN

GND

N/C

XOUT

GND

Note: ^ denotes internal pull up