LTC2910

10

2910fb

voltages fell below the exact threshold for a specified mar-

gin. All LTC2910 inputs have a relative threshold accuracy

of ±1.5% over the full operating temperature range.

For example, when the LTC2910 is programmed to moni-

tor a 5V input with a 10% tolerance, the desired UV trip

point is 4.5V. Because of the ±1.5% relative accuracy of

the LTC2910, the UV trip point is between 4.433V and

4.567V which is 4.5V ±1.5%.

the UV trip point as well. Using the example just given, if

the resistances used to set the UV trip point have 1% ac-

curacy, the UV trip range is between 4.354V and 4.650V.

This is illustrated in the following calculations.

The UV trip point is given as

VV

R

R

UV

B

A

=+

⎛

⎝⎜

⎞

⎠⎟

05

1

.•

The two extreme conditions, with a relative accuracy of

1.5% and resistance accuracy of 1%, result in

VV

R

R

a

UV MIN

B

A

()

.• .

•

•.

•.

=+

⎛

⎝⎜

⎞

⎠⎟

0 5

0 985

1

099

101

n

nd

VV

R

R

UV MAX

B

A

()

.• .

•

•.

•.

=+

⎛

⎝⎜

⎞

0 5

1 015

1

101

099

⎠⎠⎟

For a desired trip po

of

V

R

R

The

B

A

int

.

,

45

8

=

rrefore

VV

UV MIN

,

.• .

•

•

.

.

⎛

⎝⎜

05

0985

1 8

099

101

⎞⎞

⎠⎟

=

=+

4 354

05

1015

1 8

101

0

.

.• .

•

•

.

()

V

and

VV

UV MAX

..

.

99

4 650

⎛

⎝⎜

⎞

⎠⎟

=

V

Glitch Immunity

In any supervisory application, noise riding on the moni-

tored DC voltage causes spurious resets. To solve this

problem without adding hysteresis, which causes a new

error term in the trip voltage, the LTC2910 lowpass filters

the output of the first stage comparator at each input.

This filter integrates the output of the comparator before

asserting the reset output logic. A transient at the input

of the comparator of sufficient magnitude and duration

triggers the output logic. The Typical Performance Char-

acteristics section shows a graph of the Transient Duration

vs. Comparator Overdrive.

RST/⎯R⎯S⎯T Timing

holds RST and ⎯R⎯S⎯T asserted after all faults have cleared.

This assures a minimum reset pulse width allowing a

settling time delay for the monitored voltage after it has

entered the valid region of operation.

When any input drops below its designed threshold, the

⎯R⎯S⎯T pin asserts low and the RST pin asserts high. When

all inputs recover above their designed thresholds, the

reset delay timer starts. If all inputs remain above their

designed thresholds when the timer finishes, the ⎯R⎯S⎯T

pin weakly pulls high and the RST pin strongly pulls low.

However, if any input falls below its designed threshold

during this timeout period, the timer resets and restarts

when all inputs are above the designed thresholds.

Selecting the Reset Timing Capacitor

able to accommodate a variety of applications. Connecting

the timeout period. The value of capacitor needed for a

particular timeout period is:

The Reset Timeout Period vs. Capacitance graph found

in the Typical Performance Characteristics section shows

APPLICATIONS INFORMATION