Integration time

Tint

ms

Operating temperature

Top

25

50

Note:

(1) The clock frequency and the integration times must be fixed at the factory.

However, it will tolerate a slight deviation in clock frequency and integration

time as indicated by the minimum and maximum clock speeds.

(2) Clock pulse high is specified at 2.0 MHz at 25% duty.

(3) The Tint is specified with a 2.0 MHz clock frequency. In operation the time

constants in the reference generator is set to match the initial exposure time,

hence the time constant will determine the optimum integration time.

Accordingly it is highly recommended that the parameters adjusted at factory for

the specific applications.

Switching Characteristics (25°C)

The switching characteristics for the I/O clocks are shown in Figure 4, Module Timing

Diagram. The timing parametric values and their symbols are given in the Table 4.

Table 4. Switching Parameter and Timing Symbol Definition

Symbol

Min.

Typical

Max.

Units

Clock cycle time

to

0.50

µs

Clock pulse width

tw

100

ns

Clock duty cycle

25

50

%

Prohibit crossing time

of Start Pulse

tprh

15

ns

Data setup time

tds

20

ns

Data hold time

tdh

20

ns

PAGE 6 OF 9 - PI331MC-DR, 11-8-00

MODULE TIMING DIAGRAM

FIGURE 4.

CP

SP

Vanalog

Digout

to

tw

tprh

tdh

tdl

tds

tsh

tddl

tdodl