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STPMIC25 数据表(PDF) 73 Page - STMicroelectronics |
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STPMIC25 数据表(HTML) 73 Page - STMicroelectronics |
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73 / 145 page  6.2.9 Enable status register 2 (EN_SR2) Table 37. EN_SR2 7 6 5 4 3 2 1 0 EN_LDO8 EN_LDO7 EN_LDO6 EN_LDO5 EN_LDO4 EN_LDO3 EN_LDO2 EN_LDO1 R R R R R R R R • Address: 0x08 • Default: 0bxxxxxxxx where x depends on regulator status (0 = disabled, 1 = enabled) • Description: This register reflects the IP current enable status despite the setting in MAIN or ALT configurations. [7] EN_LDO8: Current internal enable status of LDO8. 0: Disabled 1: Enabled [6] EN_LDO7: Current internal enable status of LDO7. 0: Disabled 1: Enabled [5] EN_LDO6: Current internal enable status of LDO6. 0: Disabled 1: Enabled [4] EN_LDO5: Current internal enable status of LDO5. 0: Disabled 1: Enabled [3] EN_LDO4: Current internal enable status of LDO4. 0: Disabled 1: Enabled [2] EN_LDO3: Current internal enable status of LDO3. 0: Disabled 1: Enabled [1] EN_LDO2: Current internal enable status of LDO2. 0: Disabled 1: Enabled [0] EN_LDO1: Current internal enable status of LDO1. 0: Disabled 1: Enabled STPMIC25 Register descriptions DS14278 - Rev 3 page 73/145 |
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