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STPMIC25 数据表(PDF) 117 Page - STMicroelectronics |
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STPMIC25 数据表(HTML) 117 Page - STMicroelectronics |
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117 / 145 page  6.8.11 NVM BUCK mode shadow register 1 (NVM_BUCK_MODE_SHR1) Table 91. NVM_BUCK_MODE_SHR1 7 6 5 4 3 2 1 0 BUCK4_PREG_MODE[1:0 BUCK3_PREG_MODE[1:0 BUCK2_PREG_MODE[1:0 BUCK1_PREG_MODE[1:0 R/W R/W R/W R/W • Address: 0x9A • Default: Depends on the PMIC part number • Description: NVM BUCK mode shadow register 1 (see Section 5.2). [7:6] BUCK4_PREG_MODE[1:0]: 00: BUCK4 operates in high power mode (HP) 01: BUCK4 operates in low power mode (LP) 10: BUCK4 operates in forced PWM mode (CCM) 11: reserved [5:4] BUCK3_PREG_MODE[1:0]: 00: BUCK3 operates in high power mode (HP) 01: BUCK3 operates in low power mode (LP) 10: BUCK3 operates in forced PWM mode (CCM) 11: reserved [3:2] BUCK2_PREG_MODE[1:0]: 00: BUCK2 operates in high power mode (HP) 01: BUCK2 operates in low power mode (LP) 10: BUCK2 operates in forced PWM mode (CCM) 11: reserved [1:0] BUCK1_PREG_MODE[1:0]: 00: BUCK1 operates in high power mode (HP) 01: BUCK1 operates in low power mode (LP) 10: BUCK1 operates in forced PWM mode (CCM) 11: reserved STPMIC25 Register descriptions DS14278 - Rev 3 page 117/145 |
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