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数据搜索系统，热门电子元器件搜索 |
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STPMIC25APQR 数据表(PDF) 96 Page - STMicroelectronics |
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STPMIC25APQR 数据表(HTML) 96 Page - STMicroelectronics |
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96 / 145 page  6.5.7 LDOx ALTERNATE mode control register (LDOx_ALT_CR) (x = 2/5/6/7/8) Table 60. LDOx_ALT_CR 7 6 5 4 3 2 1 0 reserved BYPASS VOUT[4:0] EN R R/W R/W R/W R/W R/W R/W R/W • Address: 0x50/0x59/0x5C/0x5F/0x62 • Default: 0b0XXXXXXX where X depends on the value programmed in the NVM • Description: LDO2/LDO5/LDO6/LDO7/LDO8 ALTERNATE mode control register. This register is initialized to the default value in the CHECK&LOAD state. The user can write to these registers to control enable, bypass mode, and set the voltage of the related LDO instance, which is applied to the ALTERNATE mode (see Section 5.4.6. [7] reserved [6] BYPASS: select bypass mode operation 0: LDOx operates in normal mode 1: LDOx operates in bypass mode The default value is the same as LDOx_MAIN_CR [5:1] VOUT[4:0]: LDOx output voltage settings. See Section 4.2.6 The default value is the same as LDOx_MAIN_CR [0] EN: 0: LDOx is disabled 1: LDOx is enabled The default value is the same as LDOx_MAIN_CR STPMIC25 Register descriptions DS14278 - Rev 3 page 96/145 |
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