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STPMIC25APQR 数据表(PDF) 121 Page - STMicroelectronics |
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STPMIC25APQR 数据表(HTML) 121 Page - STMicroelectronics |
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121 / 145 page  6.8.17 NVM pull-down control shadow register 2 (NVM_PD_SHR2) Table 97. NVM_PD_SHR2 7 6 5 4 3 2 1 0 REFDDR_PD reserved BUCK7_PD[1:0] BUCK6_PD[1:0] BUCK5_PD[1:0] R/W R/W R/W R/W R/W R/W R/W R/W • Address: 0xAA • Default: Depends on the PMIC part number • Description: NVM pull-down control shadow register 2. The content of this register is copied into BUCKS_PD_CR2 in the INIT&LOAD and the CHECK&LOAD states. [7] REFDDR_PD: 0: no pull-down 1: pull-down active when REFDDR is disabled (EN = 0) [6] reserved [5:4] BUCK7_PD[1:0]: BUCK7 pull-down selection. 00: no pull-down 01: slow pull-down active when BUCK7 is disabled (EN = 0) 10: fast pull-down active when BUCK7 is disabled (EN = 0) 11: slow pull-down forced active [3:2] BUCK6_PD[1:0]: BUCK6 pull-down selection. 00: no pull-down 01: slow pull-down active when BUCK6 is disabled (EN = 0) 10: fast pull-down active when BUCK6 is disabled (EN = 0) 11: slow pull-down forced active [1:0] BUCK5_PD[1:0]: BUCK5 pull-down selection. 00: no pull-down 01: slow pull-down active when BUCK5 is disabled (EN = 0) 10: fast pull-down active when BUCK5 is disabled (EN = 0) 11: slow pull-down forced active STPMIC25 Register descriptions DS14278 - Rev 3 page 121/145 |
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