List of figures

Figure 1.

Pin connections (top view) ............................................................ 2

Figure 2.

Supply current vs. supply voltage ...................................................... 10

Figure 3.

Input offset voltage production distribution at VCC = 5 V ....................................... 10

Figure 4.

Input offset voltage production distribution at VCC = 36 V ...................................... 10

Figure 5.

Input offset voltage vs. temperature at VCC = 5 V ........................................... 10

Figure 6.

Input offset voltage vs. temperature at VCC = 36 V .......................................... 11

Figure 7.

Input offset voltage thermal drift distribution at VCC = 5 V ...................................... 11

Figure 8.

Input offset voltage thermal drift distribution at VCC = 36 V ..................................... 11

Figure 9.

Input offset voltage vs. supply voltage ................................................... 11

Figure 10.

Input offset voltage vs. common-mode voltage at VCC = 5 V .................................... 11

Figure 11.

Input offset voltage vs. common-mode voltage at VCC = 36 V ................................... 11

Figure 12.

Input bias current vs. temperature ...................................................... 12

Figure 13.

Input bias current vs. common-mode voltage at VCC = 5 V ..................................... 12

Figure 14.

Input bias current vs. common-mode voltage at VCC = 36 V .................................... 12

Figure 15.

Output current vs. output voltage at VCC = 5 V ............................................. 12

Figure 16.

Output current vs. output voltage at VCC = 36 V ............................................ 12

Figure 17.

Output saturation voltage (VOL) vs. supply voltage with RL = 10 kΩ ............................... 12

Figure 18.

Output saturation voltage (VOH) vs. supply voltage with RL = 10 kΩ............................... 13

Figure 19.

Output saturation voltage (VOL) vs. supply voltage with RL = 600 Ω ............................... 13

Figure 20.

Output saturation voltage (VOH) vs. supply voltage with RL = 600 Ω............................... 13

Figure 21.

Positive slew rate at VCC = 36 V ....................................................... 13

Figure 22.

Negative slew rate at VCC = 36 V ...................................................... 14

Figure 23.

Slew rate vs. VCC ................................................................. 14

Figure 24.

Open loop bode diagram at VCC = 5 V ................................................... 14

Figure 25.

Open loop bode diagram at VCC = 36 V .................................................. 14

Figure 26.

Closed loop bode diagram at VCC = 5 V.................................................. 14

Figure 27.

Closed loop bode diagram at VCC = 36 V ................................................. 14

Figure 28.

Phase margin vs. common-mode voltage and load current at VCC = 5 V ........................... 15

Figure 29.

Phase margin vs. capacitive load ...................................................... 15

Figure 30.

Small step response at VCC = 5 V ...................................................... 15

Figure 31.

Small step response at VCC = 36 V ..................................................... 15

Figure 32.

Desaturation from low rail at VCC = 36 V ................................................. 15

Figure 33.

Desaturation from high rail at VCC = 36 V ................................................. 15

Figure 34.

Small step overshoot vs. load capacitance ................................................ 16

Figure 35.

Linearity vs. load resistance at VCC = 5 V................................................. 16

Figure 36.

Settling time high to low at VCC = 36 V................................................... 16

Figure 37.

Settling time low to high at VCC = 36 V................................................... 16

Figure 38.

Noise vs. frequency................................................................ 16

Figure 39.

Noise vs. time at VCC = 36 V ......................................................... 16

Figure 40.

THD+N vs. output voltage at VCC = 36 V ................................................. 17

Figure 41.

CMRR vs. frequency at VCC = 12 V..................................................... 17

Figure 42.

PSRR vs. frequency at VCC = 12 V ..................................................... 17

Figure 43.

Input current limitation .............................................................. 18

Figure 44.

EMIRR on In+ and In- pins ........................................................... 19

Figure 45.

Maximum VCC for safe operation using SO8 package ........................................ 20

Figure 46.

Maximum output current for safe operation on SO8 package ................................... 21

Figure 47.

Maximum output current for safe operation on DFN8 package .................................. 21

Figure 48.

Test configuration for RISO ........................................................... 22

Figure 49.

Inverting amplifier configuration with parasitic input capacitances ................................ 22

TSB952

List of figures

DS14576 - Rev 1

page 34/36