Data Sheet

AD5122A/AD5142A

THEORY OF OPERATION

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Rev. D | 19 of 29

1 X = don’t care.

I2C SERIAL DATA INTERFACE

The AD5122A/AD5142A have 2-wire, I2C-compatible serial interfa-

ces. The device can be connected to an I2C bus as a target device,

under the control of a controller device. See Figure 3 for a timing

diagram of a typical write sequence.

The AD5122A/AD5142A supports standard (100 kHz) and fast

(400 kHz) data transfer modes. Support is not provided for 10-bit

addressing and general call addressing.

The 2-wire serial bus protocol operates as follows:

1. The controller initiates a data transfer by establishing a start

condition, which is when a high-to-low transition on the SDA

line occurs while SCL is high. The following byte is the address

byte, which consists of the 7-bit target address and an R/W

bit. The target device corresponding to the transmitted address

responds by pulling SDA low during the ninth clock pulse (this is

called the acknowledge bit). At this stage, all other devices on

the bus remain idle while the selected device waits for data to

be written to, or read from, its shift register.If the R/W bit is set

high, the controller reads from the target device. However, if the

R/W bit is set low, the controller writes to the target device.

2. Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge bit).

The transitions on the SDA line must occur during the low

period of SCL and remain stable during the high period of SCL.

3. When all data bits have been read from or written to, a stop

condition is established. In write mode, the controller pulls the

SDA line high during the tenth clock pulse to establish a stop

condition. In read mode, the controller issues a no acknowledge

for the ninth clock pulse (that is, the SDA line remains high).

The controller then brings the SDA line low before the tenth

clock pulse, and then high again during the tenth clock pulse to

establish a stop condition.

I2C Address

The facility to make hardwired changes to ADDR allows the user to

incorporate up to nine of these devices on one bus as outlined in

Table 12.

Table 12. Device Address Selection

ADDR0 Pin

ADDR1 Pin

7-Bit I2C Device Address

VLOGIC

VLOGIC

0100000

No connect1

VLOGIC

0100010

GND

VLOGIC

0100011

VLOGIC

No connect1

0101000

No connect1

No connect1

0101010

GND

No connect1

0101011

VLOGIC

GND

0101100

No connect1

GND

0101110

GND

GND

0101111

1 Not available in bipolar mode (VSS < 0 V) or in low voltage mode (VLOGIC = 1.8

V).

Write Operation

When writing to the AD5122A/AD5142A, the user must begin with

a start command followed by an address byte (R/W = 0), after

which the device acknowledges that it is prepared to receive data

by pulling SDA low.

Two bytes of data are then written to the DAC, the most significant

byte followed by the least significant byte. Both of these data bytes

are acknowledged by the AD5122A/AD5142A. A stop condition

follows. The write operations for the AD5122A/AD5142A are shown

in Figure 38.

A repeated write function gives the user flexibility to update the

device a number of times after addressing the device only once, as

shown in Figure 39.

Figure 38. AD5122A/AD5142A Interface Write Command