LD8526

08/31/2018

11

Leadtrend Technology Corporation

www.leadtrend.com.tw

LD8526-DS-00 August 2018

Pri. PWM

DRV

t

t

>1.2ms

16cycle

<1.1ms

Green mode

detection pulse

Enter

Green Mode

Leave

Green Mode

Leave

Green Mode

>1.1ms

<1.1ms

Fig. 16

Turn-on Phase

After a negative voltage (−300 mV typical) is sensed on

the DET pin, the driver output voltage (Int. DRV, see Block

Diagram) is made high and the internal MOSFET is

switched on. After switch-on of the SR MOSFET, the input

signal on the DET pin is blanked for 1.5

s (typical). This

will eliminate false switch-off due to high frequency ringing

at the start of the secondary stroke.

Turn-off Phase

The DET pin has detection gate on time to do prediction

gate pre-drop method (TON x 0.5 = TPREDICT), and adjusting

VDS decreases gate driver voltage to 4V (typical).

As soon as the DET voltage is above VDET_OFF, the

driver output is pulled to ground. For avoiding SR being

too late to turn off in CCM, the following condition must be

met, as shown in Fig. 17.

10mV

-

X

R

I

-

V

DET

DET_OFF

DET_OFF







Where IDET_OFF = 100

A, VDET_OFF = +20mV, X= thermal

effect and parasitic inductance from trace & electronic

components. Hence RDET must be from 600Ω down to

find the appropriate turn-off time.

The behavior of

Int. DRV in DCM & CCM are shown

separately in Fig. 18.

DET

+

-

Green Mode

Detect

SR_ ON

Logic

VBIAS

SR_ MOS Drain

RDET

+

-

IDET_OFF

VDET_OFF

Fig. 17

ISD

DET

t

t

Int. DRV

t

ISD

DET

t

t

Int. DRV

t

VDET_ OFF

DCM

CCM

TPREDICT

VDET_ OFF

TON

TON

TPREDICT

Fig. 18

On-Chip OTP - Auto Recovery

An internal OTP circuit is embedded inside the LD8526 to

provide the worst-case protection for this controller. When

the chip temperature rises and it

’s higher than the trip OTP

level, the output will be disabled until the chip is cooled

down below the hysteresis window.