STM6315 datasheet(7/21 Pages) STMICROELECTRONICS

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STM6315

Operation

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Operation

2.1

Reset output

The STM6315 Microprocessor Reset Circuit has an active-low, open drain reset output. This

output structure will sink current when RST is asserted. Connect a pull-up resistor from RST

to any supply voltage up to 6V (see Figure 4 on page 6). Select a resistor value large

enough to register a logic low, and small enough to register a logic high while supplying all

input current and leakage paths connected to the reset output line. A 10k pull-up is sufficient

in most applications.

The STM6315 asserts a reset signal to the MCU whenever VCC goes below the reset

threshold (VRST), or when the manual reset input (MR) is taken low (see Figure 5 and

Figure 6 on page 8). RST is guaranteed valid down to VCC = 1.0V.

During power-up, (once VCC exceeds the reset threshold) an internal timer keeps RST low

for the reset time-out period, trec. After this interval, RST returns high.

If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays

low for at least the reset time-out period. Any time VCC goes below the reset threshold, the

internal timer clears. The reset timer starts when VCC returns above the reset threshold.

2.2

Manual reset input

A logic low on MR asserts RST. RST remains asserted while MR is low, and for trec after it

returns high. The MR input has an internal pull-up resistor 63k

Ω (typ), allowing it to be left

open if not used.

This input can be driven with TTL/CMOS-logic levels or with open drain/collector outputs.

Connect a standard open push-button switch from MR to VSS to create a manual reset

function (see Figure 4 on page 6); external debounce circuitry is not required. If the device is

used in a noisy environment, connect a 0.1µF capacitor from MR to VSS to provide

additional noise immunity.

2.3

Negative-going VCC transients

The STM6315 is relatively immune to negative-going VCC transients (glitches). Figure 12 on

page 11 shows typical transient duration versus reset comparator overdrive (for which the

STM6315 will NOT generate a reset pulse). The graph was generated using a negative

pulse applied to VCC, starting at 0.5V above the actual reset threshold and ending below it

by the magnitude indicated (Reset Threshold Overdrive). The graph indicates the maximum

pulse width a negative VCC transient can have without causing a reset pulse. As the

magnitude of the transient increases (further below the threshold), the maximum allowable

pulse width decreases. Any combination of duration and overdrive which lies under the

curve will NOT generate a reset signal (see Figure 12). A 0.1µF bypass capacitor mounted

as close as possible to the VCC pin provides additional transient immunity.

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