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ADIN1300CCPZ-R7 数据表(PDF) 9 Page - Analog Devices |
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ADIN1300CCPZ-R7 数据表(HTML) 9 Page - Analog Devices |
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9 / 96 page ![]() Data Sheet ADIN1300 SPECIFICATIONS analog.com Rev. B | 9 of 96 Hardware Reset Timing Table 3. Hardware Reset Timing Parameter Description Min Typ Max Unit t1 RESET_N low time 10 μs t2 XTAL_I crystal settling time 1.5 ms XTAL_I external clock settling time 0 ms t3 Hardware configuration latch time 64 μs t4 Management interface active 5 ms Figure 3. Hardware Reset Timing Management Interface Timing Table 4. Management Interface Timing Parameter Description Min Typ Max Unit t1 MDC period 180 ns t2 MDC high time 70 ns t3 MDC low time 70 ns t4 MDC rise/fall time 5 ns t5 MDIO signal setup time to MDC 10 ns t6 MDIO signal hold time to MDC 10 ns t7 MDIO delay time to MDC 0 60 ns Figure 4. Management Interface Timing |
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