Data Sheet

ADIN2299

THEORY OF OPERATION

analog.com

Rev. D | 16 of 21

There is also an error recovery mechanism in the SPI. In the event

the SPI leader detects something wrong with the SPI link, it may

flush the link to reset low level SPI communication. A flush is

initiated by issuing a SPI transaction the length of 0 byte or 1 byte.

If a transaction with a length of 1 is issued, the byte value placed on

MOSI is ignored by the SPI follower. Similarly, the value on MISO

can be ignored. If a flush is initiated between any two read or write

operations, nothing notable happens. If a flush is initiated during a

read operation, the following notable actions are taken.

If the RREQ signal is high and no read request acknowledge

transaction has been sent, the following occurs:

►

RREQ goes low.

►

A flush at this point concludes the read operation, and the SPI

leader must not attempt to retrieve the data status header or

message data.

►

The data status header and message data that the SPI follower

prepared for transmission is discarded.

►

The SPI follower does not attempt to retransmit flushed messag-

es.

►

SPI transactions can operate normally from this point.

If the RREQ signal is high and a read request acknowledge trans-

action has been sent, the following occurs:

►

RREQ goes low.

►

A flush at this point concludes the read operation, and the SPI

leader must not attempt to retrieve the data status header or

message data.

►

The data status header and message data that the SPI follower

prepared for transmission is discarded.

►

The SPI follower does not attempt to retransmit flushed messag-

es.

►

SPI transactions can operate normally from this point.

If RREQ is inactive, the following occurs:

►

The data status header and message data that the SPI follower

prepared for transmission is discarded.

►

The SPI follower does not attempt to retransmit flushed messag-

es.

►

SPI transactions can operate normally from this point.

Figure 12. SPI Applications Processor Interface

Table 14. SPI Applications Processor Interface Balls

Mnemonic

Direction

Description

SPI0_SEL3_SS

Input

SPI0 Follower Select Input.

SPI0_CLK

Input

SPI0 Clock Input.

SPI0_MOSI

Input

SPI0 Leader Out, Follower In.

SPI0_MISO

Output

SPI0 Leader In, Follower Out.

RREQ

Output

RREQ is a signal that notifies

the application side that a

message is ready to be read.

BUSY

Output

Busy Signal. This signal

indicates to the application side

that the communication side is

busy.

Ethernet Applications Processor Interface

Selection

Figure 13 shows the Ethernet applications processor interface

direct connection through the RMII.

Figure 13. Direct Connection Through RMII

Figure 14 shows the Ethernet applications processor interface

indirect connection.