CS902-A-R datasheet(13/15 Pages) RICHTEK

13 / 15 page

Conceptual

CS902-A-R

www.richtek.com

June 13, 2013

Channel

Address

Range

Resol

ution

MTP Factory

Initialization

Value

Bit (Step)

Channel Disable

00h

0h ~ 3Fh

00h

8bits

AVDD

01h

13.5V(00h) ~ 19.8V(3Fh)

0.1V

15V(15h)

6bits (64 steps)

HVS

02h

0V(0h) ~ 3V(Fh)

0.2V

1.6V(08h)

4bits (16 steps)

AVDD OCP

(Negative offset)

03h

0A(0h) ~ 2.8A(7h)

0.4A

1.6A(04h)

3bits (8 steps)

AVDD Soft-Start

Time

04h

10ms(0h) ~ 20ms(1h)

10ms

10ms(0h)

1bits (2 steps)

Buck1 (VI/O)

05h

2.2V(0h) ~ 3.7V(Fh)

0.1V

3.3V(11h)

4bits (16 steps)

VGH_L

06h

20V(0h) ~ 35V(Fh)

33V(13h)

4bits (16 steps)

VGH_H Offset

07h

0V(0h) ~ 15V(Fh)

8V(08h)

4bits (16 steps)

GPM stop level

08h

5V(1h) ~ 15V(3h)

5V(01h)

2bits (4 steps)

VGL

09h

-13.5V(Fh) ~ -4.5V(0h)

0.6V

-6.3V(03h)

4bits

Control Register1

FFh

00h: Read data form DAC register

01h : Read data form EEPROM register

51h : Write all DAC into EEPROM

A1h: All EEPROM to DAC register

01h

8bits

Channel Disable Register (Address 00h)

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Reserved

OPAMP

0 : Enable

1 : Disable

VGH

0 : Enable

1 : Disable

VGL

0 : Enable

1 : Disable

GPM

0 : Enable

1 : Disable

NTC

0 : Enable

1 : Disable

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