2000 Mar 16

8

Philips Semiconductors

Preliminary specification

5 V mixers/oscillators and synthesizers for

cable TV and VCR 2-band tuners

TDA6502; TDA6502A;

TDA6503; TDA6503A

handbook, halfpage

UHFIN1

UHFIN2

VHFIN

RFGND

IFFIL1

IFFIL2

PVHFL

PVHFH

PUHF

FMST

SW

CE/AS

DA

CL

UHFOSCIB2

UHFOSCOC2

UHFOSCOC1

UHFOSCIB1

OSCGND

VHFOSCIB

VHFOSCOC

GND

IFOUT

VCC

XTAL

VT

CP

LOCK/ADC

1

2

3

4

5

6

7

8

9

10

11

12

13

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

TDA6502

TDA6502A

FCE570

Fig.2

Pin configuration for TDA6502 and

TDA6502A.

handbook, halfpage

UHFIN1

UHFIN2

VHFIN

RFGND

IFFIL1

IFFIL2

PVHFL

PVHFH

PUHF

FMST

SW

CE/AS

DA

CL

UHFOSCIB2

UHFOSCOC2

UHFOSCOC1

UHFOSCIB1

OSCGND

VHFOSCIB

VHFOSCOC

GND

IFOUT

VCC

XTAL

VT

CP

LOCK/ADC

1

2

3

4

5

6

7

8

9

10

11

12

13

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

TDA6503

TDA6503A

FCE571

Fig.3

Pin configuration for TDA6503 and

TDA6503A.

8

FUNCTIONAL DESCRIPTION

8.1

Control mode selection

(SDA) and serial clock (SCL) input respectively.

A HIGH level on pin SW enables the 3-wire bus: pins CE/AS, DA and CL are used as chip enable (CE), data and clock

inputs respectively.

Table 2

Bus format selection

PIN

3-WIRE BUS MODE

SYMBOL

TDA6502;

TDA6502A

TDA6503;

TDA6503A

SW

11

18

LOW-level voltage or ground

HIGH-level voltage or open-circuit

CE/AS

12

17

address selection input

enable input

DA

13

16

serial data input

data input

CL

14

15

serial clock input

clock input

LOCK/ADC

15

14

ADC input or test output

lock detector output or test output