 2004 Microchip Technology Inc.

DS21072G-page 9

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6.6

PAGE CACHE AND ARRAY MAPPING

The cache is a 64 byte (8 pages x 8 bytes) FIFO buffer.

The cache allows the loading of up to 64 bytes of data

before the write cycle is actually begun, effectively pro-

viding a 64-byte burst write at the maximum bus rate.

Whenever a write command is initiated, the cache

starts loading and will continue to load until a stop bit is

received to start the internal write cycle. The total

length of the write cycle will depend on how many

pages are loaded into the cache before the stop bit is

given. Maximum cycle time for each page is 5 ms. Even

if a page is only partially loaded, it will still require the

same cycle time as a full page. If more than 64 bytes of

data are loaded before the stop bit is given, the address

pointer will'wrap around' to the beginning of cache

page 0 and existing bytes in the cache will be overwrit-

ten. The device will not respond to any commands

while the write cycle is in progress.

6.7

Cache Write Starting at a Page

Boundary

If a write command begins at a page boundary

(address bits A2, A1 and A0 are zero), then all data

loaded into the cache will be written to the array in

sequential addresses. This includes writing across a

4K block boundary. In the example shown below,

(Figure 4-2) a write command is initiated starting at

byte 0 of page 3 with a fully loaded cache (64 bytes).

The first byte in the cache is written to byte 0 of page 3

(of the array), with the remaining pages in the cache

written to sequential pages in the array. A write cycle is

executed after each page is written. Since the write

begins at page 3 and 8 pages are loaded into the

cache, the last 3 pages of the cache are written to the

next row in the array.

6.8

Cache Write Starting at a Non-Page

Boundary

When a write command is initiated that does not begin

at a page boundary (i.e., address bits A2, A1 and A0

are not all zero), it is important to note how the data is

loaded into the cache, and how the data in the cache is

written to the array. When a write command begins, the

first byte loaded into the cache is always loaded into

page 0. The byte within page 0 of the cache where the

load begins is determined by the three least significant

address bits (A2, A1, A0) that were sent as part of the

write command. If the write command does not start at

byte 0 of a page and the cache is fully loaded, then the

last byte(s) loaded into the cache will roll around to

page 0 of the cache and fill the remaining empty bytes.

If more than 64 bytes of data are loaded into the cache,

data already loaded will be overwritten. In the example

shown in Figure 7-2, a write command has been initi-

ated starting at byte 2 of page 3 in the array with a fully

loaded cache of 64 bytes. Since the cache started load-

ing at byte 2, the last two bytes loaded into the cache

will'roll over' and be loaded into the first two bytes of

page 0 (of the cache). When the stop bit is sent, page

0 of the cache is written to page 3 of the array. The

remaining pages in the cache are then loaded sequen-

tially to the array. A write cycle is executed after each

page is written. If a partially loaded page in the cache

remains when the STOP bit is sent, only the bytes that

have been loaded will be written to the array.

6.9

Power Management

This design incorporates a power standby mode when

the device is not in use and automatically powers off

after the normal termination of any operation when a

stop bit is received and all internal functions are com-

plete. This includes any error conditions, ie. not receiv-

ing an acknowledge or stop condition per the two-wire

monitor circuitry to prevent inadvertent writes (data cor-

tor circuitry is powered off when the device is in standby

mode in order to further reduce power consumption.